Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2000-11-16
2004-06-08
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C438S113000
Reexamination Certificate
active
06747337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor wafer and a semiconductor device (or an integrated circuit chip) formed by cutting the semiconductor wafer.
2. Description of the Background Art
A silicon substrate in the form of wafer (hereinafter, referred to simply as “silicon wafer”) is generally used for manufacturing semiconductor devices (integrated circuits). In the device manufacturing process, a dislocation called “slip” may occur in the silicon wafer while it is subjected to high-temperature processing. If such a slip extends into an integrated circuit, the circuit will suffer failures like increased leakage and dielectric breakdown.
In the studies of the slips, the applicant has found that a sip is normally formed from the peripheral of the silicon wafer and extends inwards along its crystal orientation. For example, the slip tends to extend in a <110> direction in the silicon wafer of <100> surface orientation.
More specifically, the applicant has found that the formation of slip
4
is detected, as shown in
FIG. 5
, both at a notch
2
that is provided in the silicon wafer
1
primarily for recognition of the surface orientation of the wafer, and at a contact point
8
of silicon wafer
1
and a boat
7
that is used to secure silicon wafer
1
within a reaction chamber during the high-temperature processing.
FIGS. 6 and 7
are enlarged views of formation of slips
4
in the conventional silicon wafer
1
.
As shown in
FIGS. 6 and 7
, a number of integrated circuits
6
are formed in silicon wafer
1
, and dicing lines
5
are provided to surround the integrated circuits
6
. Silicon wafer
1
is divided along dicing lines
5
into a plurality of integrated circuit chips.
In the conventional silicon wafer
1
, however, integrated circuits
6
have been arranged without taking into consideration the formation of slips
4
. Thus, as shown in
FIGS. 6 and 7
, slips
4
would extend into integrated circuits
6
. This causes device failures including increased leakage and dielectric breakdown, and results in a poor yield.
SUMMARY OF THE INVENTION
The present invention is directed to solve the above-described problems. An object of the present invention is to suppress extension of a slip into an integrated circuit to improve the yield.
The semiconductor wafer according to an aspect of the present invention has a notch for recognition of crystal surface orientation, and a dicing line is aligned with a defect extending from the notch such that the dicing line overlaps the defect. A typical example of the defect is a dislocation (slip) that occurs during high-temperature processing of the wafer.
By placing the dicing line as described above, the defect such as dislocation extends within the dicing line and is prevented from extending into the integrated circuit.
The dicing line preferably extends from an end of the notch towards the inside of the semiconductor wafer.
Thus, the dislocation extending from the end of the notch comes to lie within the dicing line, so that extension of the dislocation into the integrated circuit is prevented.
The semiconductor wafer according to another aspect of the present invention is secured to a boat during high-temperature processing, and a dicing line is aligned with a defect extending from a contact point of the boat and the semiconductor wafer such that the dicing line overlaps the defect.
In this aspect again, the defect comes to lie within the dicing line, so that the defect is prevented from entering within the integrated circuit.
The dicing line preferably extends from the contact point towards the inside of the semiconductor wafer.
Thus, the dislocation extending from the contact point comes to lie within the dicing line, and extension of the dislocation into the integrated circuit is prevented.
The semiconductor wafer is a silicon wafer of <100> surface orientation and the dicing line is made to extend in a <110> direction.
In the silicon wafer of <100> surface orientation, a dislocation tends to extend in the <100> direction. Thus, by making the dicing line extend in the <100> direction, the dislocation comes to he within the dicing line.
The semiconductor device according to the present invention is formed by cutting the semiconductor wafer along the dicing line.
With the semiconductor wafer as described above, it is possible to effectively prevent extension of a dislocation or the like into an integrated circuit region. Thus, there exist almost no defects as described above in the semiconductor devices (or the integrated circuit chips) obtained by cutting the semiconductor wafer. Therefore, the semiconductor device according to the present invention is highly reliable.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
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Kimura Yasuhiro
Yamamoto Hidekazu
Le Thao X.
McDermott & Will & Emery
Pham Long
Renesas Technology Corp.
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