Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2001-02-26
2003-01-28
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S690000, C438S706000, C438S759000, C438S928000, C438S976000, C438S977000
Reexamination Certificate
active
06511895
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor wafer processing apparatus for grinding a semiconductor wafer to thin it.
DESCRIPTION OF THE PRIOR ART
In a process for manufacturing a semiconductor wafer for use in a semiconductor device, grinding is performed to decrease the thickness of the semiconductor wafer as thin semiconductor devices are becoming predominant. The grinding is carried out by mechanical grinding of a back side of the semiconductor wafer opposite to its face side after a circuit pattern has been formed on the face side. On the surface of the semiconductor wafer after mechanical grinding, there is a damaged layer embrittled by microcracks formed by mechanical grinding. The damaged layer is known to include the microcracks and impair the fracture strength of the semiconductor wafer. Thus, a conventional semiconductor has been used with such a thickness that the semiconductor is not affected by a decrease in the fracture strength due to the damaged layer.
In response to the light weight and compact size of electronic equipment, moves for thinning semiconductor devices to meet demands for their light weight and compact size have become brisk. Along this line, further thinning of semiconductor wafers has also been demanded. To reduce the thickness of the semiconductor wafer, however, the influence of the decrease in the fracture strength due to the damaged layer is becoming nonnegligible. To solve this problem, processing to a small thickness (hereinafter referred to as thinning), including removal of the damaged layer, is necessary. However, any appropriate apparatus, which can perform a series of thinning steps, ranging from mechanical grinding of the semiconductor wafer to removal of the damaged layer, has not existed.
SUMMARY OF THE INVENTION
Under these circumstances, the present invention aims to provide a semiconductor wafer processing apparatus and a semiconductor wafer processing method which can perform a series of thinning steps, ranging from mechanical grinding of a semiconductor wafer to removal of its damaged layer.
According to the present invention, there is provided a semiconductor wafer processing apparatus for grinding a surface of a semiconductor wafer to thin the semiconductor wafer, comprising a grinding portion for mechanically grinding the semiconductor wafer, a wafer cleaning portion for cleaning the semiconductor wafer after mechanical grinding, a damaged layer removal treatment portion for removing a damaged layer, caused to the semiconductor wafer by mechanical grinding, after cleaning by the wafer cleaning portion, and a wafer transport mechanism for transferring the semiconductor wafer between the grinding portion, the wafer cleaning portion, and the damaged layer removal treatment portion.
It is preferred to include a precenter portion for centering the semiconductor wafer, and supply the semiconductor wafer, which has been centered by the precenter portion, to the grinding portion by the wafer transport mechanism. A stocker can be provided for accommodating the semiconductor wafer before processing which is to be supplied to the grinding portion and/or the semiconductor wafer after processing which has been withdrawn from the damaged layer removal treatment portion. The wafer transport mechanism preferably includes a robot mechanism on a polar coordinate system. Preferably, the wafer transport mechanism also includes a before-cleaning transport portion for withdrawing the semiconductor wafer after mechanical grinding from the grinding portion, and passing the semiconductor wafer on to the wafer cleaning portion, and an after-cleaning transport portion for withdrawing the semiconductor wafer after cleaning from the wafer cleaning portion, and passing the semiconductor wafer on to the damaged layer removal treatment portion. The damaged layer removal treatment portion may be a plasma treatment portion for etching the damaged layer by plasma treatment. The damaged layer removal treatment portion may be a wet etching treatment portion for etching the damaged layer with a chemical liquid. Preferably, the wafer transport mechanism comprises a first wafer transport portion for holding the semiconductor wafer from the precenter portion and bringing the semiconductor wafer onto the grinding portion, a second wafer transport portion for withdrawing the semiconductor wafer ground by the grinding portion and transporting the semiconductor wafer to the wafer cleaning portion, and a third wafer transport portion having a robot mechanism on a polar coordinate system for transferring the semiconductor wafer between the precenter portion, the wafer cleaning portion, and the damaged layer removal treatment portion, and the damaged layer removal treatment portion is disposed in a third quadrant and a fourth quadrant of an orthogonal coordinate system in which an origin of the polar coordinate system of the robot mechanism is a common origin and a direction of the grinding portion is a Y-axis positive direction, and such that the origin of the polar coordinate system is positioned on a line of extension of a semiconductor wafer carry-in and carry-out center line of the damaged layer removal treatment portion. The stocker for accommodating the semiconductor wafer before processing which is to be supplied to the grinding portion and/or the semiconductor wafer after processing which has been withdrawn from the damaged layer removal treatment portion is preferably provided at a position at which the wafer can be brought in and brought out by the third wafer transport portion. The cleaning portion can be disposed in one of the first quadrant and the second quadrant of the orthogonal coordinate system. The precenter portion can be disposed in a quadrant of the coordinate system on a side opposite to the cleaning portion, with the Y-axis of the coordinate system being interposed between the precenter portion and the cleaning portion.
According to the present invention, there is further provided a semiconductor wafer processing method for thinning a semiconductor wafer to a target thickness, including the steps of mechanically grinding a side of the semiconductor wafer opposite to a surface thereof, where a circuit has been formed, by a grinding portion; withdrawing the semiconductor wafer after mechanical grinding from the grinding portion, and passing the semiconductor wafer on to the wafer cleaning portion; cleaning the semiconductor wafer passed on to the wafer cleaning portion; withdrawing the semiconductor wafer after cleaning from the wafer cleaning portion and passing the semiconductor wafer on to a damaged layer removal treatment portion; and removing a damaged layer, caused by the mechanical grinding, in the damaged layer removal treatment portion.
The damaged layer removal treatment portion may be a plasma treatment portion for etching the damaged layer by plasma treatment. It is preferred to grind the semiconductor wafer by mechanical grinding to a thickness being a sum of the target thickness and a dry etching margin set in a range of 3 &mgr;m to 50 &mgr;m, and remove a remainder of the semiconductor wafer by dry etching using plasma treatment. The semiconductor wafer may consist essentially of silicon. After the semiconductor wafer is ground by the mechanical grinding, the semiconductor wafer is preferably cleaned with a liquid before dry etching is performed. The liquid may be water. The damaged layer removal treatment portion may be a wet etching treatment portion for etching the damaged layer with a chemical liquid. Preferably, mechanical grinding and removal of the damaged layer are performed, with a protective film being formed on the surface of the semiconductor wafer where the circuit has been formed.
REFERENCES:
patent: 5693182 (1997-12-01), Mathuni
patent: 6159827 (2000-12-01), Kataoka
El-Kareh, “Fundamentals of Semiconductor Processing Technologies”, Chapter 5, pp. 282-285, Kluwer(1995).
Arita Kiyoshi
Haji Hiroshi
Iwai Tetsuhiro
Koma Yutaka
Disco Corporation
Sarkar Asok Kumar
Sherry Michael
Smith , Gambrell & Russell, LLP
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