Semiconductor wafer testing structure

Details Semiconductor wafer testing structure Semiconductor wafer testing structure

1998-03-10

2001-08-14

Chaudhuri, Olik (Department: 2814)

Implements or apparatus for applying pushing or pulling force

Vehicle-body lifters

Cable hoist

C257S094000

Reexamination Certificate

active

06273400

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to the field of electrical device testing at the wafer level. It is particularly directed to laser testing at the wafer level, and more particularly to high frequency testing of Vertical Cavity Surface Emitting Lasers (VCSELs).
BACKGROUND OF THE INVENTION
The term electrical device as used herein includes devices having electrical inputs and/or outputs, devices having optical inputs and/or outputs, and devices having electro-optical inputs and/or outputs. Thus, although the description is directed to VCSELs the inventive concept is meant to be used with any electrical device.
Performance testing of semiconductor lasers is important during the water manufacturing phase in order to ascertain the lasers operability and its meeting particular specifications. It is advantageous to be able to validate the performance as early as possible so as to remove faulty wafers from further processing. A VCSEL semiconductor laser permits a first level of testing at the wafer level. VCSEL technology is described in a paper entitled “Progress in Planarized Vertical Cavity Surface Emitting Laser Devices and Arrays,” by Morgan et al., SPIE, Vol. 1562, pp. 149-159, 1991, which is incorporated herein by reference.
A prime using candidate of VCSEL diode technology is data communication. In data communications, as in some other technologies, the high frequency characteristics of the diode laser are extremely important. The characteristics include rise and fall times, bandwidth, relaxation oscillation frequency, and small and large signal response. The wafer level testing techniques employed to date are not usable at high frequencies due to the long return path that the laser current has to travel. The severity of this problem is illustrated in FIG.
1
.
FIG. 1
shows a typical dosed test loop for testing the performance of a laser on a wafer. The wafer diameter is typically three to four inches. It is noted that the maximum test frequency is inversely proportional to the physical length of the electrical circuit's wire return path. A long return path reduces the maximum test frequency. The return path starts at the point the wafer test probe
80
makes contact with the top diode contact
10
, usually the anode. The laser diode
15
is located along the wafer cross section
25
. The return path continues through the diode's active region
20
, and out through the substrate
30
. The substrate
30
is generally in contact with a chuck or wafer holder
40
which acts as a common ground contact. The loop is dosed with a wire
50
connected to the test signal source
60
and returns through a second wire
70
attached to the probe
80
. The test current must travel several inches through the electrical circuit's test loop. The long electrical wire represents a significant high impedance inductance that severely limits high frequency testing with the probe
80
. The present invention is a method and apparatus to enable high frequency testing and overcome this limitation.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a structure and method for testing an electrical device contained within a wafer. It is particularly directed where the structure is a bias-tee, and more particularly directed where the electrical device is a VCSEL.
It is a particular object of the present invention to provide a structure comprising a water having an electrical device contained within itself. The electrical device has a top layer stack which provides a connection for an AC/DC bias-tee electrode, an active region, and a bottom layer stack which provides a connection for a DC-only bias-tee electrode. A conductive plate is formed across the top layer stack. A semi-insulating region is formed in the top layer stack between the conductive plate and the bottom layer stack. The conductive plate provides a connection for an AC-only bias-tee electrode. The present invention is especially concerned with the case where the top and bottom layer stacks are respectively the top and bottom mirror layer stacks associated with an electrical device that is a laser.
It is another particular object to provide a structure for testing an electrical device contained within a wafer. The electrical device has a top ohmic contact on a top layer stack and a bottom contact on a bottom layer stack. A capacitor is formed across the top layer stack An AC source is connected across the top ohmic contact and the capacitor. A DC source is connected across the top ohmic contact and the bottom contact. The electrical device is capable of producing an output having characteristics responsive to the AC and DC sources. A means is provided for measuring the output characteristics.
It is still another particular object to provide a method comprising the steps of: providing a wafer containing an array of electrical devices, in which each of the electrical devices has a top mirror layer stack forming a first electrode, a bottom mirror layer stack forming a second electrode; electrically connecting a first electrical device contact to the first electrode; electrically connecting a second electrical device contact to the second electrode; forming a conductive plate across the top mirror layer stack which forms a third electrical device contact; implanting a semi-insulating region residing in the top mirror layer stack between the conductive plate and the bottom layer stack. A variation of the method includes a step for reducing the height of part of the top mirror layer stack to bring the conductive plate in closer proximity to the lower mirror layer stack.


REFERENCES:
patent: 5047711 (1991-09-01), Smith et al.
patent: 5335106 (1994-08-01), Paquin et al.
patent: 5500867 (1996-03-01), Krasulick

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