Semiconductor wafer testing method and apparatus

Details Semiconductor wafer testing method and apparatus Semiconductor wafer testing method and apparatus

1998-03-10

1999-04-06

Bowers, Charles

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Having diverse electrical device

438 16, 438 18, H01S 3103

Patent

active

058917462

ABSTRACT:
The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.

REFERENCES:
patent: 5024966 (1991-06-01), Dietrich et al.
patent: 5034334 (1991-07-01), Flynn et al.
patent: 5396068 (1995-03-01), Bethea
W. Ruska, "Microelectronic Processing", McGraw-Hill, pp. 374-383 (no month given), 1987.

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