Semiconductor wafer, semiconductor device, and process for...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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C257S620000, C438S361000

Reexamination Certificate

active

07042063

ABSTRACT:
A semiconductor wafer is disclosed in which a high concentration impurity layer is formed in a semiconductor wafer to a predetermined depth, in order to electrically connect electrodes formed on the principal face of the wafer without forming trenches and through holes in the wafer. An n++diffusion region is formed in the dicing region of a semiconductor wafer by ion implanting or diffusion. The diffusion region extends to an n++layer formed deep in the semiconductor wafer. The width of the n++diffusion region is made wide enough to account for the blade width of a dicer, so that an n++diffusion region remains at the outer periphery of each of the chips divided by the dicing operation. Bump electrodes on the wafer surface electrically connect with the n++layer deep in the semiconductor through the n++diffusion region.

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patent: 2001/0028083 (2001-10-01), Onishi et al.
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patent: 2000-277542 (2000-10-01), None

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