Semiconductor wafer-scale integrated device composed of intercon

Pulse or digital communications – Repeaters – Testing

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357 72, 357 59, 357 68, H01L 2702, H01L 2704, H01L 2710

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049070622

ABSTRACT:
A device equivalent to a wafer-scale integrated device is achieved by employing multiple IC chips installed on a silicon wafer. For fabricating the device, conventional IC chips of necessary different types are prepared, having their aluminum-wired surfaces coated with a silicon nitride film. These IC chips are placed on a substrate made of silicon keeping the wired faces face up. The wafer may be provided with depressions in which the chips are placed for precise positioning. Upon these chips and the wafer, a silicon layer is grown by a PVD method. The grown silicon layer fills gaps between the IC chips and binds the chips to each other and to the wafer, forming a single piece of wafer. Excessively grown silicon which is taller than the chips is removed by mechano-chemical polishing until the silicon nitride surfaces are exposed. During this polishing process, the silicon nitride film protects the wired surfaces from mechanical and chemical damage. The silicon nitride film is chemically removed until the aluminum wirings are exposed. An insulating layer and aluminum patterning are formed upon the exposed IC chips and filled gaps to form multi-layer wirings for interconnecting the chips and forming input/output connections. This method allows low cost wafer-scale integration higher density wirings and good heat-removal.

REFERENCES:
patent: 3588632 (1971-06-01), Nakata
patent: 3607466 (1971-09-01), Miyazaki
patent: 3624467 (1971-11-01), Bean et al.
patent: 3666548 (1972-05-01), Brack et al.
patent: 3871007 (1975-03-01), Wakamiya et al.
patent: 3894893 (1975-07-01), Kabaya et al.
patent: 4057824 (1977-11-01), Woods
patent: 4074342 (1978-02-01), Honn et al.
patent: 4466181 (1984-08-01), Takishima
Patent Abstracts of Japan, vol. 8, No. 235, Oct. 27, 1984 & JP-A-59 117 250.

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