Semiconductor wafer processing method of forming channel stops a

Details Semiconductor wafer processing method of forming channel stops a Semiconductor wafer processing method of forming channel stops a

1992-10-20

1993-08-31

Fourson, George

Fishing, trapping, and vermin destroying

437 28, 437 35, 437 52, H01L 2176

Patent

active

052408744

ABSTRACT:
A semiconductor device isolation method of forming a channel stop in a semiconductor wafer comprises: a) selectively forming field oxide on a semiconductor wafer surface, the field oxide having a bird's beak region and a non-bird's beak region, the bird's beak region laterally extending into a desired region on the wafer; b) masking the bird's beak region and desired region; c) with the masking in place, ion implanting a selected material into the wafer through the non-bird's beak region of the field oxide to define a channel stop implant in the wafer under the non-bird's beak region of the field oxide, such non-bird's beak region implant being conducted at an implant angle along the bird's beak which is less than about 10.degree. from perpendicular relative to the wafer surface; and d) with the masking in place, ion implanting a selected material into the wafer through the bird's beak region of the field oxide to define a channel stop implant in the wafer under and along the bird's beak region of the field oxide, such bird's beak region implant being conducted at an implant angle along the bird' s beak region which is greater than about 10.degree. and less than about 40.degree. from perpendicular relative to the wafer surface.

REFERENCES:
patent: 5173438 (1992-12-01), Sandhu
Hori, T. "1/4-pm LATID (Large Tilt-angle Implanted Drain) Technology for 3.3-V Operation", VLSI Technology Research Laboratory, (1989) pp. 32.4.1-32.4.4 (Japan).
Hori, et al., "A New Submicron MOSFET with LATID Structure", Basic Research Laboratory, pp. 15-16 (Japan), 1988.
Nagatomo, et al., "A High Density 4M DRAM Process Using Folded Bitline Adaptive Side-Wall Isolated Capacitor (FASIC) Cell", LSI R and D Lab., pp. 144-147 (Japan) IEDM 1986.
Sunouchi, et al., "Process Integration for 64M DRAM Using An Asymmetrical Stacked Trench Capacitor (AST) Cell", ULSI Research Center, Toshiba Corp., (1990) pp. 647-650 (Japan).
Fuse, et al., "A Practical Trench Isolation Technology With A Novel Planarization Process", Matsushita Electric Industrial Co., (1987) pp. 732-735.

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