Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
2011-08-30
2011-08-30
Le, Thao X (Department: 2892)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
C257SE21001, C257SE21032, C257SE21318, C257SE21321, C257SE21335, C257SE21349, C257SE21122, C257SE27141
Reexamination Certificate
active
08008107
ABSTRACT:
Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered. Multicrystalline semiconductor wafers having grain boundaries with impurities may also undergo the annealing and gettering of dispersed defects to the grain boundaries, further increasing the semiconductor substrate purity levels.
REFERENCES:
patent: 4062102 (1977-12-01), Lawrence et al.
patent: 4561171 (1985-12-01), Schlosser
patent: 4878988 (1989-11-01), Hall et al.
patent: 5298449 (1994-03-01), Kikuchi
patent: 5738942 (1998-04-01), Kubota et al.
patent: 5927131 (1999-07-01), Kiuchi et al.
patent: 6040211 (2000-03-01), Schrems
patent: 6071753 (2000-06-01), Arimoto
patent: 6093882 (2000-07-01), Arimoto
patent: 6133119 (2000-10-01), Yamazaki
patent: 6261860 (2001-07-01), Nagata
patent: 6852371 (2005-02-01), Sopori
patent: 7244306 (2007-07-01), Kurita et al.
patent: 2002/0101576 (2002-08-01), Shabani et al.
patent: 2004/0107648 (2004-06-01), Sung
patent: 2005/0126627 (2005-06-01), Hayashida
patent: 2005/0158969 (2005-07-01), Binns et al.
patent: 2006/0000414 (2006-01-01), Mercaldi et al.
patent: 2006/0130738 (2006-06-01), Kurita et al.
patent: 2006/0289091 (2006-12-01), Buonassisi et al.
patent: 2008/0157241 (2008-07-01), Kirscht et al.
patent: 0466014 (1992-01-01), None
patent: 09260392 (1997-10-01), None
patent: 2005057054 (2005-03-01), None
patent: WO-0178133 (2001-10-01), None
“European Application Serial No. 07868140.0, Extended European Search Report mailed on Mar. 2, 2011”, 6 Pgs.
Kirscht Fritz
Linke Dieter
Ounadjela Kamel
Rakotoniana Jean Patrice
Calisolar, Inc.
Jones Eric W
Le Thao X
Schwegman Lundberg & Woessner, P.A.
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