Semiconductor wafer package, method and apparatus for connecting

Details Semiconductor wafer package, method and apparatus for connecting Semiconductor wafer package, method and apparatus for connecting

1996-02-29

1999-08-31

Karlsen, Ernest

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324758, G01R 1073, G01R 3128

Patent

active

059458348

ABSTRACT:
A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

REFERENCES:
patent: 4833402 (1989-05-01), Boegh-Peterson
patent: 5148103 (1992-09-01), Pasiecznik, Jr.
patent: 5219765 (1993-06-01), Yoshida et al.
patent: 5317255 (1994-05-01), Suyama et al.

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