Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-09-16
2001-11-27
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S758010, C324S760020
Reexamination Certificate
active
06323663
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology for simultaneously testing a plurality of integrated circuits formed on a semiconductor wafer in a wafer condition.
Advances in size reduction and cost reduction of recent electronic components incorporating semiconductor IC (integrated circuit) devices are so remarkable that requirements to the size reduction and cost reduction of the semiconductor IC devices are becoming more severe.
In general, a manufacturing of a semiconductor IC device is as follows. First of all, a semiconductor chip and a lead frame are electrically connected with each other by means of a bonding wire. Thereafter, the semiconductor chip is sealed by resin or ceramic and then mounted on a printed board. However, the requirements of reducing the size of an electronic component have introduced a method of directly mounting on a circuit board a semiconductor IC device in a bare chip or chip condition to guarantee quality at low cost. The bare chip or chip condition generally represents a condition of semiconductor IC device which is just cut off a semiconductor wafer.
In order to guarantee quality of bare chips, it is necessary to execute a burn-in screening of a semiconductor IC device in the wafer condition.
However, the burn-in screening of the semiconductor wafer is complicated in handling the semiconductor wafer; thus, the requirement to low cost could not be satisfied. Furthermore, executing the burn-in screening of the plural bare chips on a semiconductor wafer is time-consuming since it requires to execute the burn-in screening separately and repeatedly one by ene or group by group. Thus, in view of time and cost, it does not bring practical merits.
Accordingly, it is earnestly required to realize a simultaneous execution of the burn-in screening of all the bare chips in the wafer condition.
FIG. 32
is a schematic view showing a testing method of a semiconductor wafer using a conventional prober. As shown in
FIG. 32
, a semiconductor wafer
202
is fixed on a wafer stage
201
provided in the prober. A probe card
204
, having probe needles
203
, - - - ,
203
made of for example tungsten, is disposed above the semiconductor wafer
202
. These probe needles
203
, - - - ,
203
are brought into contact with IC terminals on the semiconductor wafer
202
, so that an electric power voltage or signal can be supplied to the integrated circuit by means of a tester or the like to detect an output signal from the integrated circuit chip by chip. For testing the same kind of integrated circuits in a short time, a full automatic prober is normally used since it has an alignment function and is capable of automatically executing a measurement of chip one by one. In
FIG. 32
, a reference numeral
205
represents a wiring pattern and a reference numeral
206
represents an external electrode terminal.
Hereinafter, a conventional testing method of a semiconductor wafer using a full automatic prober will be explained with reference to
FIGS. 32 and 33
.
First of all, in a step SB
1
, the semiconductor wafer
202
is automatically transported from a wafer carrier onto the wafer stage
201
. Next, in a step SB
2
, positioning of the semiconductor wafer
202
is carried out using a CCD camera or the like so that IC terminals on the semiconductor wafer
202
can be brought into contact with the probe needles
203
, - - -
203
. Then, in a step SB
3
, the wafer stage
201
is shifted below the probe card
204
so that the semiconductor wafer
202
is placed below the probe card
204
.
Subsequently, in a step SB
4
, the probe needles
203
, - - - ,
203
are brought into contact with the IC terminals on the semiconductor wafer
202
. An electric power voltage or signal is applied to the integrated circuit to measure an output signal from the integrated circuit, thereby executing a test of the integrated circuit. After finishing the test of one integrated circuit, the wafer stage
201
is shifted to the next integrated circuit. Then, the probe needles
203
, - - - ,
203
are brought into contact with the terminals of the next integrated circuit to execute a measurement of the next integrated circuit.
According to the conventional testing method of a semiconductor wafer using a full automatic prober, a plurality of integrated circuits on the semiconductor wafer
202
are successively measured in the manner above-described. When the test of all the integrated circuits is completed, the semiconductor wafer
202
is returned from the wafer stage
201
to the wafer carrier in a step SB
5
. For a plurality of semiconductor wafers
202
, - - - ,
202
, above-described steps are repeatedly executed to accomplish a measurement of each semiconductor wafer
202
. When the measurement of all the semiconductor wafers
202
is finished, operation of the full automatic prober ends.
A method of shortening a test time per chip would be, for example, to provide a self test circuit (i.e. BIST circuit) to execute the burn-in screening (high-speed operation) of memories such as DRAM by means of a prober.
Executing the burn-in screening processing in the wafer condition according to the previously-described testing method of a semiconductor wafer using a prober would require a time not longer than 1 minute in total for the shifting of the semiconductor wafer
202
in the procedures of the steps SB
1
, SB
3
and SB
5
and the positioning of the semiconductor wafer
202
in the step SB
2
. However, the burn-in screening in the step SB
4
usually requires several to several tens hours. The conventional testing method of a semiconductor wafer using a prober is disadvantageous in that it necessitates to test semiconductor wafers one by one. Accordingly, it takes an extremely long time to test a great amount of semiconductor wafers. This will results in a huge increase of cost for manufacturing an LSI chip.
Another disadvantage of the testing operation using an automatic prober is an exclusive usage of the probe during tests, because the alignment function cannot be used for tests for other kinds of semiconductor wafers or other purposes.
Providing a BIST circuit for shortening a test time per chip, applied to DRAM or the like, leads to an increase of a chip area and reduces the number of chips per wafer, thus causing a problem of increasing chip cost.
To execute the burn-in screening of bare chips at a time in the wafer condition, it is necessary to simultaneously apply an electric power voltage or signal to a plurality of chips formed on the same wafer, to operate all of these plural chips. To this end, it will be necessary to prepare a probe card having numerous probe needles (e.g. several thousands or more). However, the conventional needle type probe card cannot meet such a need in view of great number of pins and cost increase.
Proposed to solve such a problem is a thin film type probe card having bumps on a flexible substrate (Refer to Nitto Technical Reports Vol. 28, No. 2 (October 1990) PP. 57-62)
Hereinafter, the burn-in screening using a flexible substrate with bumps will be explained.
FIGS.
34
(
a
) and
34
(
b
) are cross-sectional views illustrating the probing condition when a flexible substrate with bumps is used. In FIGS.
34
(
a
) and
34
(
b
), a reference numeral
211
represents a probe card which comprises a polyimide substrate
218
, a wiring layer
217
formed on the polyimide substrate
218
, bump electrodes
216
, - - - ,
216
, and a through hole wiring connecting the wiring layer
217
and the bump electrodes
216
, - - - ,
216
.
As illustrated in FIG.
34
(
a
), the probe card
211
is pushed against a semiconductor wafer
212
serving as a tested substrate so that a pad
215
on the semiconductor wafer
212
is electrically connected to a corresponding bump
216
of the probe card
211
. If testing condition is in a room temperature, a test will be feasible in this condition by simply applying an electric power voltage or signal to the bump
216
via the wiring layer
217
.
However, a diameter of the semiconductor wafer
212
possibly increases
Fujiwara Atsushi
Hashimoto Shin
Hatada Kenzou
Miyanaga Isao
Nakata Yoshirou
Karlsen Ernest
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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