Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2001-12-11
2004-06-01
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S690000, C438S691000
Reexamination Certificate
active
06743698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor wafer having few undulation components, which components may cause problems especially in device-processing steps, and a method for producing such a semiconductor wafer.
2. Description of Related Art
With recent use of higher integration degree of semiconductor devices, requirement for flatness of semiconductor wafer surface to be used has also become increasingly severer. In particular, when a semiconductor wafer is chucked on a wafer chuck, while warpage of the wafer may be corrected, irregularities present on the back surface of the wafer may be transferred to the front surface to deteriorate flatness of the front surface. Further, if such a wafer chuck has irregularities on its holding surface, such irregularities may also be transferred to the wafer front surface, and deteriorate production yield in the device-processing steps. Therefore, in order to improve the flatness of semiconductor wafers, flatness of their back surfaces and the wafer chuck surface must be improved in addition to flatness of the wafer front surfaces.
Conventional methods for producing semiconductor wafers generally comprise, as shown in
FIG. 4
as a block diagram of process steps, a slicing step (A) to obtain a wafer of thin disc shape by slicing a single crystal ingot grown in a crystal pulling apparatus by means of a wire saw, inner diameter slicer or the like; a chamfering-step (B) to chamfer a peripheral edge portion of the wafer obtained through the slicing step (A) to prevent cracking or breakage of the wafer; a lapping step (C) to flatten the surface of the chamfered wafer by lapping it; an etching step (D) to remove mechanical damages of the chamfered and lapped wafer; a mirror polishing step (E) to finish the etched wafers to have a mirror polished surface by polishing so that surface roughness and flatness of the wafer should be improved; and a cleaning step (F) to clean the mirror polished wafer to remove the polishing agent or dust particles from the wafer.
Wafers to be polished in such a method as mentioned above usually have irregularities generated in the etching step on their front surfaces or back surfaces. When such a wafer is held at its one side (back surface) by chucking (vacuum chucking) and the other side (front surface) is polished, the surface to be polished would have irregularities reflecting the irregularities of the back surface, and polishing should be done for such a surface. Therefore, while a flat surface of the wafer with no irregularities may be obtained when the polishing is completed and the wafer is still held by chucking, the front surface would have irregularities transferred from the back surface when the wafer is released from the holding. Thus, the irregularities of wafer back surface are transferred to the front surface, which invites various problems in the device-processing steps as described above.
These phenomena have been understood in their nature, but it has not been elucidated at all what kind of irregularities of wafer back surface or holding front surface of wafer chuck are actually transferred to the front surface and cause problems.
As for the flatness of semiconductor wafers, while there have not been any definite definitions or specifications, the following three kinds of components, i.e., periodic irregularities having a wavelength of about 20 mm or more called warpage, irregularities having a wavelength of around several mm to 20 mm called undulations (waviness), irregularities having a wavelength of about 100 &mgr;m or less called microroughness, have conventionally been considered important. In particular, the components called undulations have been understood as images obtained by the principle of magic mirror, and they have been confirmed only externally, and thus could not be evaluated quantitatively.
In addition, the photolithography techniques used in the recent device-processing steps have shifted from those utilizing entire surface light exposure to those utilizing partial light exposure (stepper method), and therefore the flatness concerning the undulation components has become more important. Moreover, considering the current situation that STI (Shallow Trench Isolation) has become to be widely used as a device isolation technique in the device-processing steps, planarization by CMP (Chemical Mechanical Polishing) is important to form STI, and hence it is necessary to eliminate the undulation components in order to surely isolate devices by obtaining uniform polishing stock removal.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the aforementioned problems, and its object is to quantitatively evaluate the undulation components of semiconductor wafers, thereby providing a semiconductor wafer free from the undulation components. Such undulation components may be, if present, transferred from the wafer back surface to the front surface to cause problems upon photolithography in the device-processing step, device isolation and the like as described above. Another object of the present invention is to provide a method for producing such a semiconductor wafer, and a wafer chuck therefor.
To achieve the aforementioned object, the present invention provides a semiconductor wafer characterized in that it has undulation components on wafer back surface of 10 &mgr;m
3
or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm.
According to the present invention, front surface and back surface profiles of semiconductor wafers are determined before and after the wafer holding by vacuum suction, and the determined profiles are analyzed by frequency analysis to quantitatively evaluate the influence of the back surface profile on the front surface profile in relation to the spatial frequency. The characteristic of the aforementioned semiconductor wafer is defined based on such analysis and evaluation.
That is, if a semiconductor wafer has undulation components on its back surface of 10 &mgr;m
3
or less represented in terms of power spectrum density (PSD) at least for such components at a wavelength of 10 mm, the back surface profile of the wafer would not be transferred to the front surface to cause problems upon photolithography and the like, even when, for example, the wafer is held on a wafer chuck by chucking.
The present invention also provides a semiconductor wafer characterized in that it has undulation components on its wafer front surface of 10 &mgr;m
3
or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm.
Because the transfer of the back surface profile to the front surface is prevented according to the present invention, the wafer front surface can have a power spectrum density of 10 &mgr;m
3
or less as defined in the aforementioned wafer, for example, even when the wafer is held on a wafer chuck by chucking.
The present invention also provides a semiconductor wafer characterized in that it has undulation components on its wafer front surface and back surface of 10 &mgr;m
3
or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm.
According to the present invention, there can be provided such a wafer excellent in the flatness as defined above, which is free from the undulation components of the back surface, and therefore free from the undulation components of the front surface transferred from the back surface.
The present invention further provides a semiconductor wafer characterized in that it exhibits a variation of power spectrum density of 2.0 or less for undulation components at a wavelength of from 3 mm to 20 mm of wafer back surface and/or wafer front surface.
The term “variation of power spectrum density for undulation components at a wavelength of from 3 mm to 20 mm” herein used means a value calculated in accordance with the following equation: [log(PSD at wavelength of 20 mm)−log(PSD at wavelength of 3 mm)]. When th
Tsunoda Hitoshi
Ushiki Takehito
Deo Duy-Vu
Hogan & Hartson L.L.P.
Norton Nadine G.
Shin-Etsu Handotai & Co., Ltd.
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