Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2001-03-27
2002-10-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S928000
Reexamination Certificate
active
06465328
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a manufacturing method, which produces a semiconductor wafer of high flatness, and low process deformation from a single crystal ingot. For example, this manufacturing method comprises a process, wherein a wafer is sliced from a single crystal ingot, then subjected to surface grinding and finish grinding on both sides at the same time, undergoes low-deformation edge rounding using a fixed abrasive, polished on both sides simultaneously, and is subjected to edge-rounded polishing, after which it is finish polished again on one side. That is, the present invention relates to a manufacturing method, which performs low deformation grinding and polishing of an edge-rounded portion between surface grinding and polishing, and produces a high-precision semiconductor wafer, with high flatness, and low process deformation required by large-diameter quality wafers, making it possible to enhance yields in the device process.
BACKGROUND OF THE INVENTION
In general, a semiconductor wafer manufacturing method comprises the following processes.
1) A slicing process, which produces a thin, disc-shaped wafers by slicing a single-crystal ingot pulled by a single-crystal pulling apparatus;
2) An edge rounding process for preventing the wafer chipping and cracking;
3) A lapping process for planarizing a wafer that has undergone edge rounding;
4) An etching process, which removes a process deformed layer generated on a wafer by the above-mentioned processing;
5) An edge-rounded portion polishing process, which finish polishes the edge-rounded portion;
6) A polishing process, which polishes the above-mentioned wafer on either one side or both sides; and
7) A process, which finish polishes the above-mentioned wafer.
In the past, in the above-mentioned etching process, acid etching was performed. However, this acid etching made it difficult to maintain the flatness achieved via the lapping process, and because of the abundant waste liquid in the treatment processes of both etching and lapping, there were numerous environmental issuesas well.
Accordingly, with an object of doing away with the lapping process and etching process, and eliminating such waste liquid treatment, there has been proposed (Japanese Patent Laid-open No. 6-177096) a method for surface grinding each side of a wafer following slicing.
Further, with an objective of reducing the manufacturing process time, reducing polishing costs (quantity), and enhancing wafer flatness, there has been proposed (Japanese Patent Laid-open No. 8-316180) a method, which after slicing, subjects a wafer to edge rounding, two-sided surface grinding, and then uses chemical polishing to finish the wafer. And with the same objective, there has been proposed (Japanese Patent Laid-open No. 9-248740) a method, which after slicing, subjects a wafer to two-sided surface grinding, performs etching as needed to remove residual deformation, and then uses chemical polishing to finish both sides of the wafer.
Furthermore, with an objective of simplifying the wafer manufacturing process, and enhancing wafer flatness, there has been proposed (Japanese Patent Laid-open No. 9-260314, Japanese Patent Laid-open No. 9-270396) a method, which after slicing, subjects a wafer to edge rounding and one-sided surface grinding, performs etching as needed to remove residual deformation, washes the wafer, and then uses chemical polishing to finish both sides of the wafer. Also there has been proposed (Japanese Patent Laid-open No. 9-260314) a method, which after slicing, subjects a wafer to edge rounding, one-sided surface grinding, lapping, then after performing dry etching, uses chemical polishing to finish both sides of the wafer.
As described above, a variety of manufacturing methods have been proposed with an objective of solving problems related to waste liquid treatment for etchants and lapping agents, and for reducing processing time and also polishing costs when manufacturing semiconductor wafers.
However, even with the above-mentioned proposals, in methods, in which an end rounding process is performed after the slicing process, because the thickness of the sliced wafers varies, the bevel width varies over the entire wafer perimeter, causing yields to drop in the fabrication process.
Further, in methods, in which a lapping process and two-sided surface grinding process are carried out following an edge rounding process, there is the danger that the edge-rounded portion of a wafer will be scratched by the inner wall of the carrier, and at the same time, because of the different thickness of the wafers being processed, a wafer will collide with a carrier during grinding, causing the edge-rounded portion to be chipped and damaged, and causing the loss of the cross-sectional shape of the edge-rounded portion.
SUMMARY OF THE INVENTION
With the foregoing problems of wafer manufacturing methods in view, it is an objective of the present invention to attempt to increase the precision of a wafer by incorporating a low-deformation grinding process into the wafer manufacturing process. Further, an objective of the present invention is to provide a novel high-precision semiconductor wafer manufacturing method, which is capable of reducing total materials costs, and especially, which enables the realization of the high degree of flatness and low process deformation required by large-diameter wafers, and enhances yields in the device process.
The inventors undertook a variety of studies concerning grinding and polishing processes, having as an objective the realization of a high degree of flatness and low process deformation in a semiconductor wafer, and enhance yields in the device process. As a result, the inventors learned that it is possible to achieve the above-mentioned objective in a semiconductor wafer manufacturing method. A wafer is sliced from a single crystal ingot, mirror polished on a required side by performing a surface grinding process of various processes, followed by applying a mirror finish process of various processes for making the edge-rounded portion of a wafer a mirror finish with low deformation. Then finally finish polished on a required main side of an edge-rounded wafer.
Further, the inventors learned that various processes can be applied. Such as, 2-stage processes to each of the above-mentioned surface grinding process, an edge-rounded portion mirror finish process, and a process for mirror finish polishing a required main surface, which are employed in the process of the present invention. Furthermore, the inventors brought the present invention to completion based on the knowledge that it is possible to achieve the above-mentioned object more efficiently by interposing an edge-rounded portion grinding and polishing process between the surface grinding process and the process for mirror finish polishing a required main surface.
REFERENCES:
patent: 6162730 (2000-12-01), Kai et al.
Hashii Tomohiro
Masuda Sumihisa
Onizaki Kazunori
Breiner & Breiner L.L.C.
Nhu David
Sumitomo Metal Industries Ltd.
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