Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2006-11-22
2011-11-29
Pham, Thanh V (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S619000, C257SE21599, C438S018000, C438S033000, C438S068000, C438S114000
Reexamination Certificate
active
08067819
ABSTRACT:
The present invention discloses a semiconductor wafer having a scribe line dividing the semiconductor wafer into a matrix of plural semiconductor chips. The semiconductor wafer includes a polysilicon layer, a poly-metal interlayer insulation film formed on the polysilicon layer, and a first metal wiring layer formed on the poly-metal interlayer insulation film. The semiconductor wafer includes a process-monitor electrode pad formed on a dicing area of the scribe line. The process-monitor electrode pad has a width greater than the width of the dicing area. The process-monitor electrode pad includes a contact hole formed in the poly-metal insulation film for connecting the first metal wiring layer to the polysilicon layer.
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Oct. 6, 2010 European search report in connection with counterpart European patent application No. 06833675.
Kouno Satoshi
Yoshida Masaaki
Cooper & Dunham LLP
Ligai Maria
Pham Thanh V
Ricoh & Company, Ltd.
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