Semiconductor wafer having distortion-free alignment regions

Details Semiconductor wafer having distortion-free alignment regions Semiconductor wafer having distortion-free alignment regions

1997-03-31

2000-01-11

Whitehead, Jr., Carl W.

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

257350, 257351, 257353, 257370, 257347, H01L 23544

Patent

active

060139544

ABSTRACT:
A semiconductor wafer having an SOI (Silicon-On-Insulator) structure and capable of being accurately aligned without undesirable contrast appearing in an infrared transmission image. The wafer is implemented as a laminate SOI wafer including an SOI layer. An aligning oxide film pattern and an oxide film pattern are buried in the SOI layer. The aligning oxide film pattern and oxide film pattern are respectively aligned with an aligning mask pattern and a mask pattern provided on a masking quartz wafer. In this condition, the laminate wafer is subjected to preselected processing. One of opposite major surfaces of the SOI wafer facing the quartz wafer is smoothed over its regions containing at least the aligning oxide film pattern and through which infrared rays are to be transmitted with respect to photoresist. The other major surface is smoothed over the above regions by having a polycrystal silicon film thereof removed.

REFERENCES:
patent: 5294823 (1994-03-01), Eklund et al.
patent: 5315144 (1994-05-01), Cherne

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