Semiconductor wafer, handling apparatus, and method

Details Semiconductor wafer, handling apparatus, and method Semiconductor wafer, handling apparatus, and method

1997-12-19

1999-04-06

Chaudhuri, Olik

Metal working

Barrier layer or semiconductor device making

148 332, 414936, 118732, 438680, 438758, B65G 4907, H01L 2168

Patent

active

058902694

ABSTRACT:
A semiconductor wafer comprising a single crystalline lattice suitable for use in the manufacture of integrated circuits, namely computer chips and dies, wherein a diameter of the wafer is greater than approximately 150 millimeters and wherein the wafer includes a first hole extending through the wafer. The hole is adapted to facilitate handling of the wafer without directly contacting a surface of the wafer. The wafer preferably includes a primary flat and the first hole includes a flat side having a predetermined and known orientation with respect to the primary flat of the wafer. In one embodiment, the wafer further includes a guide hole formed near the first hole such that the center-points of the first hole and the guide hole are oriented with a predetermined and known orientation with respect to the primary flat of the wafer.

REFERENCES:
patent: 4306731 (1981-12-01), Shaw
patent: 4473455 (1984-09-01), Dean
patent: 4779877 (1988-10-01), Shaw
patent: 5046909 (1991-09-01), Murdoch

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