Semiconductor wafer fabrication with improved control of interna

Details Semiconductor wafer fabrication with improved control of interna Semiconductor wafer fabrication with improved control of interna

1988-02-11

1989-07-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG4, 148DIG24, 148DIG60, 148DIG71, 357526, 437 12, 437 19, 437174, 437942, 437980, 437248, H01L 21306, H01L 21322

Patent

active

048513580

ABSTRACT:
The concentration of internal gettering sites within a semiconductor wafer is controlled by two-step thermal processing. In a concentration reduction phase, the wafer is rapidly heated to an elevated temperature in the range from about 900.degree. to 1350.degree. C., resulting in the partial or total dissolution of precipitable impurities within the wafer. In a concentration enhancement step, the wafers are subjected to a relatively low temperature anneal process where the density of potential internal gettering sites is increased. By properly controlling the processing temperatures and treatment times, the two steps may be performed in either order to obtain wafers having internal gettering site concentrations within a desired range.

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