Semiconductor wafer fabrication process including gettering util

Details Semiconductor wafer fabrication process including gettering util Semiconductor wafer fabrication process including gettering util

1995-05-25

1998-08-18

Fourson, George R.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

And gettering of substrate

438439, 438471, H01L 2176

Patent

active

057958092

ABSTRACT:
An improved method of silicon wafer fabrication suitable for either CMOS and/or NMOS process flows. The present method utilizes few processing steps to reduce fabrication costs and enhance wafer throughput. The improved method combines sacrificial oxide growth and removal steps of CMOS and NMOS front end pre-oxide steps with existing pad oxide growth and removal steps, resulting in fewer required operations. The thermal cycles required to form gettering sites within Cz bulk silicon wafers are retained, thus allowing the number of required processing operations to be reduced without negatively impacting existing levels of expected production yields.

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Wolf, et al., "Silicon Processing for the VLSI Era," vol. 2, pp. 428-431.
Wolf, et al., "Silicon Processing for the VLSI Era," vol. 2, pp. 327-337.

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