Semiconductor wafer evaluation method

Details Semiconductor wafer evaluation method Semiconductor wafer evaluation method

2000-07-07

2001-05-01

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

With measuring or testing

C438S014000, C438S017000, C148SDIG001

Reexamination Certificate

active

06225137

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for evaluating a semiconductor wafer, and more particularly relates to a method for evaluating a semiconductor wafer where pinholes in an oxide film embedded in an SOI (Silicon On Insulator) wafer are measured and evaluated.
Semiconductor wafers having an SOI structure (hereinafter referred to as “SOI wafers”) have attracted great attention due to their anticipated high device integration, low power consumption and high-speed. Typical SOI wafers are a bonded type and a SIMOX (Separation by Implanted Oxygen) type. With SIMOX type SOI wafers, oxygen is not injected into the wafer due to the influence of particles attached to the wafer surface during oxygen ion implantation when making the wafer, and parts of the silicon therefore remain within the embedded oxide film. The embedded oxide film is therefore not formed, with portions where the silicon remains being referred to as pinholes. The presence of a pinhole can cause the embedded oxide film withstand voltage to be deficient, and is a direct cause of falls in the device yield. Evaluation of pinhole defects is defined in specification “SOI Wafer Standards Specification JEIDA-50-1997” published by JEIDA as one aspect of SOI wafer quality management.
The corporate body of the Japan Electronic Industrial Development Association (JEIDA) endorses a Cu detection method (Cu decoration method) and a MOS capacitor method as pinhole defect evaluation methods. In the Cu detection method, Cu is deposited on an SOI layer on top of the pinholes of weak insulating properties by electrolysis employing a CuSO
4
solution and the Cu deposits are then measured using a microscope to obtain the pinhole density of the embedded oxide film. In the MOS capacitor method, a MOS capacitor is formed on the SOI wafer, and the defective capacitor rate is obtained by measuring the withstand voltage characteristic value. There is also another method of calculating pinhole density of an embedded oxide film using MOS capacitor electrode surface area and defective-capacitor rate.
However, with the Cu detection method, an electrolyzer is necessary for handling the Cu solvent etc., but introduction in semiconductor factories and research establishments has been difficult due to the fear of devices becoming contaminated with Cu. The precision of the MOS capacitor method as an evaluation method is high, but it is necessary to form devices on the wafer. In any of these methods, preparation until wafer evaluation is implemented requires a substantial amount of time.
SUMMARY OF THE INVENTION
Implementation of a semiconductor evaluation method capable of easily counting and evaluating pinholes within an embedded oxide film of a SIMOX type SOI wafer is therefore desired.
The semiconductor wafer evaluation method of the present invention therefore comprises the steps of: preparing a substrate embedded with an oxide film; removing the oxide film from a surface of the substrate so as to expose a silicon layer; removing silicon portions within the silicon film and the embedded oxide film by etching so as to form holes within the embedded oxide layer in a first etching step; removing the silicon below the holes by etching in a second etching step; and measuring and evaluating the holes enlarged by the first and second etching steps.


REFERENCES:
patent: 2000031255 (2000-01-01), None

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