Semiconductor wafer device having separated conductive...

Details Semiconductor wafer device having separated conductive... Semiconductor wafer device having separated conductive...

2005-09-06

2005-09-06

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Groove

C257S759000, C257S760000, C257S761000, C257S762000, C257S758000, C174S261000, C174S256000, C174S257000, C428S209000, C428S210000

Reexamination Certificate

active

06940150

ABSTRACT:
A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.

REFERENCES:
patent: 5587344 (1996-12-01), Ishikawa
patent: 6376363 (2002-04-01), Iguchi
patent: 6379782 (2002-04-01), Iguchi et al.
patent: 11265866 (1999-09-01), None
patent: 2000124216 (2000-04-01), None

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