Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
2002-07-12
2004-04-20
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S052000, C438S067000, C438S107000, C438S456000
Reexamination Certificate
active
06723579
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor wafer comprising a plurality of micro-machined components, and in particular, though not limited to such a semiconductor wafer comprising micro-mirrors, and the invention also relates to a method for fabricating the semiconductor wafer.
BACKGROUND TO THE INVENTION
Semiconductor wafers comprising a plurality of micro-machined components are well known. Additionally, semiconductor wafers which comprise a plurality of micro-machined micro-mirrors are also well known. For example, U.S. Pat. No. 6,201,631 of Graywell discloses such a semiconductor wafer and also a method for fabricating such a wafer. In general, the micro-mirrors of such semiconductor wafers are arranged in a matrix array formed by a plurality of spaced apart rows and spaced apart columns. Any number of micro-mirrors may be provided, for example, a sixteen by sixteen array of two hundred and fifty-six micro-mirrors is commonly provided. Indeed, it is known to provide micro-mirror arrays of array sizes of two by two arrays up to one thousand by one thousand arrays and even greater.
Typically, such semiconductor wafers comprising an array of micro-mirrors comprise a support substrate, typically a base substrate and a component substrate which are bonded together. The component substrate comprises a handle layer which supports a membrane layer in which the micro-mirrors are formed. Cavities are formed in the handle layer for exposing the micro-mirrors through the handle layer. Typically, a buried oxide layer is located between the membrane layer and the handle layer, and after etching of the cavities in the handle layer the oxide layer adjacent the micro-mirrors is etched for exposing the micro-mirrors through the cavities in the handle layer. Electrodes are formed on the base substrate at appropriate locations, so that when the component substrate is bonded to the base substrate the electrodes are appropriately aligned with the corresponding micro-mirrors through the cavities in the handle layer, for co-operating with the micro-mirrors for tilting thereof.
The handle layer acts as a spacer for spacing the membrane layer with the micro-mirrors formed therein apart from the base substrate, and in turn the electrodes formed thereon for facilitating tilting of the micro-mirrors. The depth by which the handle layer spaces the membrane layer from the base substrate is largely determined by the area of the mirrors, and the maximum angle of tilt required. However, in general, it is desirable that the spacing between the membrane layer and the base substrate should be relatively small so that the electrodes on the base substrate are relatively close to the micro-mirrors, thereby minimising the voltages required on the electrodes for tilting the mirrors. Typically, desired spacings between the base substrate and the membrane layer are in the range of 10 &mgr;m to 200 &mgr;m. This requires that the handle layer which is supporting the membrane layer must be machined to a depth of between 10 &mgr;m and 200 &mgr;m, depending on the desired spacing, prior to bonding to the base substrate. This results in a serious problem in that in general, it is desirable that the handle layer should be of a depth of at least 350 &mgr;m, and preferably 500 &mgr;m for supporting the membrane layer until the membrane layer is otherwise supported, for example, by the base substrate. Thus, by having to reduce the depth of the handle layer to between 10 &mgr;m to 200 &mgr;m there is a considerable risk of damage to the membrane layer and the micro-mirrors while the membrane layer is supported only by the thin handle layer, until the component layer is bonded to the base substrate. This is undesirable.
There is therefore a need for a semiconductor wafer comprising a plurality of micro-mirrors, or indeed, any other micro-machined components which overcomes this problem. There is also a need for a method for fabricating a semiconductor wafer having a plurality of micro-mirrors or other micro-machined components which similarly overcomes the problem.
The present invention is directed towards providing such a semiconductor wafer and a method.
SUMMARY OF THE INVENTION
According to the invention there is provided a semiconductor wafer comprising a support substrate and a component substrate carried on the support substrate, the component substrate comprising:
a membrane layer having a plurality of spaced apart micro-machined components formed therein,
a handle layer supporting the membrane layer and having a plurality of cavities corresponding to the micro-machined components extending through the handle layer to the respective corresponding micro-machined components,
the support substrate having a first surface facing in a first direction and defining a second surface facing in a second direction away from and opposite to the first direction, the support substrate defining an intermediate surface at a level intermediate the first and second surfaces and facing in the second direction, the support substrate comprising:
a plurality of spaced apart pedestals extending in the second direction from the intermediate surface into respective corresponding ones of the cavities in the handle layer of the component substrate, each pedestal terminating in the second surface spaced apart from the corresponding micro-machined component for accommodating movement of the micro-machined component,
at least one electrode carried on the second surface of each pedestal for co-operating with the corresponding micro-machined component,
a plurality of electrically conductive addressing tracks on one of the first and the intermediate surfaces of the support substrate for carrying address signals to be conducted to the respective electrodes, and
an electrical conductor corresponding to each electrode extending through a corresponding via through the corresponding pedestal from the electrode to a corresponding one of the addressing tracks on the support substrate for conducting the corresponding address signal to the corresponding electrode.
In one embodiment of the invention a plurality of mutually insulated electrodes are carried on each pedestal, and each electrode is connected to the corresponding one of the addressing tracks on the support substrate by the corresponding one of the electrical conductors extending through the corresponding one of the vias.
Preferably, the addressing tracks on the support substrate communicate the corresponding electrodes on the pedestals with a plurality of corresponding mutually insulated addressing terminals for addressing the electrodes. Advantageously, the support substrate comprises a terminal carrier extending in the second direction from the intermediate surface for carrying the addressing terminals, and an electrical conductor corresponding to each addressing terminal extends from the corresponding addressing terminal through a corresponding via through the terminal carrier to the corresponding one of the addressing tracks on the support substrate for communicating the addressing terminal with the corresponding addressing track. Advantageously, the terminal carrier terminates in the second surface, and the addressing terminals are located on the second surface.
In one embodiment of the invention the addressing tracks are located on the first surface of the support substrate, and preferably, the vias through the respective pedestals extend to the first surface for accommodating the corresponding electrical conductors therethrough to the addressing tracks. Alternatively or additionally, the addressing tracks are located on the intermediate surface of the support substrate, and the vias through the respective pedestals extend to the intermediate surface for accommodating the corresponding electrical conductors to the addressing tracks.
In one embodiment of the invention the handle layer defines a first surface of the component substrate, the first surface of the component substrate facing in the first direction, and the component substrate being carried on the support
Blackstone Scott Carlton
Brown Stephen Alan
Gormley Colin Stephen
Analog Devices Inc.
Gauthier & Connors LLP
Mulpuri Savitri
LandOfFree
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