Semiconductor wafer assemblies

Details Semiconductor wafer assemblies Semiconductor wafer assemblies

2000-04-24

2001-11-20

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S645000, C257S634000, C257S635000, C257S637000, C257S644000

Reexamination Certificate

active

06320246

ABSTRACT:

TECHNICAL FIELD
The invention pertains to semiconductor processing etch methods, and to semiconductor assemblies comprising indicator atoms.
BACKGROUND OF THE INVENTION
Semiconductor wafer fabrication processes frequently involve etching to remove a material. For example, semiconductor fabrication processes can include etching through an insulative material to form a contact opening to an electrical node underlying the insulative material. Semiconductive wafer fabrication processes can also include, for example, etching through conductive materials, and/or etching through semiconductive materials.
An example prior art etch process is described with reference to
FIGS. 1-4
. Referring to
FIG. 1
, a semiconductive wafer fragment
10
comprises a substrate
12
and three electrical components,
14
,
16
and
18
, overlying substrate
12
. Component
14
can comprise, for example, a substrate diffusion region, and components
16
and
18
can comprise, for example, conductive lines. Substrate
12
can comprise, for example, monocrystalline silicon lightly doped with a background p-type dopant. To aid in interpretation of the claims that follow, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.
An electrically insulative material
20
is provided over electrical components
14
,
16
, and
18
. Insulative material
20
can comprise, for example, borophosphosilicate glass (BPSG).
Etch stop caps
22
and
24
are provided over conductive components
16
and
18
, respectively. Etch stops caps
22
and
24
comprise a material which is selectively etchable relative to insulative material
20
. If insulative material
20
comprises BPSG, the etch stop material can comprise, for example, silicon nitride.
A patterned photoresist
26
is provided over insulative material
20
and defines a plurality of locations
28
wherein openings are to be etched through insulative material
20
. The openings are intended to expose conductive component
14
, and etch stop caps
22
and
24
. The openings are not intended to extend through caps
22
and
24
.
Referring to
FIG. 2
, an etch is conducted to remove material
20
from locations
28
. If material
20
comprises BPSG, such etch can comprise, for example, a plasma etch utilizing CF
4
/CHF
3
. The etch is intended to be selective for material
20
relative to photoresist
26
, and relative to etch stop caps
22
and
24
. However, even a highly selective etch will remove some of the material of caps
22
and
24
, and some of photoresist
26
, during removal of material
20
.
Etch depth is typically estimated from the duration of an etch. Such estimation leaves uncertainty as to when exactly the etch reaches component
14
. Accordingly, the duration of the etch is generally allowed to be somewhat longer than that estimated to be necessary for reaching component
14
, to ensure that component
14
is in fact actually reached. However, detrimental effects can occur if the etch duration is too long.
Referring to
FIG. 3
, wafer fragment
10
is illustrated after too long of an etch duration. Such etch duration has caused an overetch into component
14
, and has undesirably removed photoresist layer
26
(FIG.
2
). After removal of photoresist layer
26
, portions of layer
20
that were intended to be protected by photoresist layer
26
are undesirably subjected to etching. This results in an undesired reduction in thickness of such portions of layer
20
. Also, the too long duration of the etch has undesirably resulted in etching through layers
22
and
24
to expose components
16
and
18
.
It would be desirable to avoid the detrimental effects illustrated in FIG.
3
. Accordingly, it would be desirable to develop new methods for determining etch rate in situ, and for ascertaining when an etch has reached a particular depth within a material.
FIG. 4
illustrates a semiconductive wafer
30
which can comprise wafer fragment
10
. Wafer
30
has a center region
32
and an edge region
34
. Typically, an etch process will comprise etching within both of regions
32
and
34
, as well as etching within portions of wafer
30
between regions
32
and
34
. A difficulty occurs in maintaining a uniform etch rate in edge region
34
relative to center region
32
. The uniformity of the etch rate in region
32
relative to that in region
34
is referred to as “center-to-edge uniformity”.
Presently, the center-to-edge uniformity of an etch process is estimated prior to the etching process, and then determined from measurements taken after the etching process. Accordingly, there is uncertainty regarding the center-to-edge uniformity during the etch process. To compensate for the uncertainty regarding the center-to-edge uniformity, etch processes are typically conducted for durations longer than what is necessary to reach a desired level within an etched material. Such long etch durations can cause the detrimental effects shown in FIG.
3
. Accordingly, it would be desirable to develop methods for reducing uncertainties regarding center-to-edge uniformity during etch processes. Specifically, it would be desirable to develop methods for ascertaining center-to-edge uniformity during etch processes.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a method of etching. A material is formed over a substrate. The material comprises a lower portion near the substrate and an upper portion above the lower portion. A quantity of detectable atoms is provided within the material. The detectable atoms are provided at a different concentration in the lower portion than in the upper portion. The material is etched and an etching debris is formed. The detectable atoms are detected in the debris.
In another aspect, the invention encompasses a method of monitoring center-to-edge uniformity of an etch occurring on a semiconductor wafer assembly. A semiconductor wafer substrate having a center and an edge is provided. A material comprising detectable atoms is formed over the substrate. The material is etched and etching debris is formed. The detectable atoms are detected in the debris. A degree of center-to-edge uniformity of the etching is determined from the detecting.
In yet another aspect, the invention comprises a semiconductor wafer assembly comprising a semiconductor wafer substrate and alternating first and second layers over the semiconductor wafer substrate. The alternating layers comprise at least one first layer and at least one second layer. The first layer comprises a first material and the second layer comprising a second material. The second material comprises atoms selected from the group consisting of yttrium, lanthanides, actinides, calcium, magnesium, and mixtures thereof.


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