Semiconductor wafer alignment tools

Details Semiconductor wafer alignment tools Semiconductor wafer alignment tools

2000-02-24

2001-07-10

Font, Frank G. (Department: 2877)

Optics: measuring and testing

By alignment in lateral direction

C356S401000, C438S401000, C430S022000

Reexamination Certificate

active

06259525

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor wafer alignment methods and to semiconductor wafer alignment tools.
BACKGROUND OF THE INVENTION
Integrated circuits are typically formed through a number of steps which include patterning and etching various features over a substrate. A necessary requirement imposed on the patterning and etching of substrate features is that such features be aligned relative to other features on the substrate. Failure to achieve adequate alignment can render a fabricated device inoperative.
One way of maintaining alignment during a fabrication process, which often involves forming multiple layers over a substrate and aligning each of the layers to one or more other layers, is to use so-called alignment or registration marks. Alignment or registration marks are typically provided over a scribe area of a wafer between individual die area. Alignment or registration marks can be provided on a substrate through utilization of a mask which contains not only alignment mark patterns, but also integrated circuitry patterns as well. One past practice has been to expose the entire mask, including the integrated circuitry patterns, to lithographic processing, and then inspect the transferred alignment patterns for alignment. If the alignment patterns were not desirably aligned, the alignment process was repeated by removing the patterned layer, re-applying and patterning it, and then inspecting for alignment. For example, a layer of photoresist will typically be formed over a substrate. A mask will be utilized to form a pattern over the photoresist, which photoresist is subsequently developed to provide alignment marks over the substrate, as well as integrated circuitry patterns. If the alignment marks are not desirably aligned, the photoresist is removed, reapplied (which can include time-consuming baking), reexposed, redeveloped and examined for misalignment again. Needless to say, removal, reapplication, reexposure, redevelopment, and reexamination of the photoresist takes precious production time and reduces throughput of the wafers.
This invention arose out of concerns associated with improving the methods through which integrated circuitry devices are formed, and in particular, with providing improved wafer alignment methods and tools.
SUMMARY OF THE INVENTION
In one embodiment, a photomask is provided having a set of alignment pattern openings and circuitry openings formed therethrough With the photomask, the substrate is first photoexposed through one of the set of alignment pattern openings and the circuitry openings, and not the other. After the first exposing, the substrate is second exposed through the other of the openings on the photomask. In another embodiment, a latent image of an alignment pattern is formed and received by a masking layer over a substrate. The position of the latent image of the alignment pattern is inspected relative to an underlying layer of material over the substrate. Alignment is ascertained through inspection of the latent image relative to the underlying layer of material. In another embodiment, an undeveloped photoresist layer is formed over a substrate. The undeveloped photoresist is exposed to processing conditions effective to form an image of an alignment pattern received over the undeveloped photoresist over a wafer scribe area. The image of the alignment pattern received by the undeveloped photoresist is inspected relative to an underlying substrate structure over the scribe area and alignment information is ascertained therefrom. In a preferred embodiment, if an alignment error is detected, the error can be corrected in real time, and the substrate further processed without reapplication of a masking layer or photoresist layer.


REFERENCES:
patent: 5601957 (1997-02-01), Mizutani et al.
patent: 5656182 (1997-08-01), Marchman et al.
patent: 5879842 (1999-03-01), Okino
patent: 5925937 (1999-07-01), Jost et al.

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