Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1999-07-26
2001-08-14
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
Reexamination Certificate
active
06274940
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor wafer processing, and more particularly to a method and apparatus that preserves alignment targets when planarizing a wafer during chemical mechanical polishing.
BACKGROUND OF THE INVENTION
Recent developments in the field of semiconductor wafer fabrication have led to advancements in the size reduction of devices present on die of a semiconductor wafer. Such advancements have led to increasing density of circuit elements in the die structure. As feature sizes and devices become smaller, there is a need to more precisely align the photolithographic masks with the wafer during masking steps, minimizing misalignment between layers.
A typical alignment technique will require the use of alignment targets that are defined on a wafer layer preceding the layer to be deposited. With recent microcircuit devices of semiconductor wafers, a large number of patterns are deposited in multiple layers comprising patterned regions of insulative, conductive and differing conductivity materials. For multiple layers, where successive metallized layers are separated by an insulation layer such as an oxide layer, there is a need to align the topography of each layer over the previous layers.
One way involves the use of alignment patterns comprising an array of alignment markings that are defined on the wafer on each previous layer. In order to ensure alignment between successive layers, it becomes necessary to replicate the positioning of the alignment markings from one layer to the next. The placement of successive circuit structures, in layers, is dependent on the precise placement of a photolithographic mask and the alignment markings on the previous layer.
Another way involves the use of alignment patterns comprising alignment marks, or markings, that are defined on the wafer on an original base layer, with all subsequent layers being aligned with respect to these alignment marks.
In order to fabricate integrated circuit structures on a wafer, a series of metallized and insulative layers are formed successively on the wafer, with the aid of alignment markings. Typically, each pair of metallized layers is separated by an insulative layer such as an oxide layer. The use of alignment markings when depositing the layers ensures alignment between layers, enabling replication of a desired topography from layer to layer.
One such system uses a step-and-repeat aligner with a reticle, or partial mask for a single chip, to form each individual die on a wafer, successively across the wafer. Individual fields are mapped across a face of the wafer for receiving a dedicated die. Each field receives a dedicated alignment marking for aligning the die within the field.
In order to prevent flaws or discontinuities in overlying metallized layers of each die, it is desirable to planarize the underlying surface of the die to make it as flat as possible. In practice, the entire wafer surface is planarized prior to depositing a metallized layer onto each of the die on the wafer face. Typically, the layer being planarized comprises an insulative layer.
One presently favored planarization technique is chemical mechanical polishing (CMP). More particularly, chemical mechanical polishing is being widely accepted as the preferred process for planarizing dielectrics and subsequently tungsten (W) plugs. One particular -use has been in the manufacture of 0.25 micrometer (and smaller) features. It has been found that process performance for oxide and tungsten chemical mechanical polishing can depend on the underlying patterns of the wafer being polished.
For cases where an array of vias (filled or unfilled) are present, or where underlying patterns are not present, dishing of the oxide layer being polished can occur. Dishing refers to the difference in elevation of oxide remaining for areas with and without underlying topography, or features. For the case of oxide chemical mechanical polishing, the oxide layer present over topography within the wafer is being planarized. The amount, or depth, of planarization is found to decrease as the distance from the underlying topography increases. Hence, it has been found in practice that the local oxide erosion rate is variable, and is dependent on the proximity to underlying features within the wafer. In close proximity with and above the underlying features, the amount of dishing is found to be minimized.
One problem with dishing is the damage that can occur to alignment targets which can potentially cause an inability to properly align subsequent layers on a die being deposited atop a wafer.
Therefore, there is a need to provide a method for minimizing the effects of dishing when preparing a wafer by way of chemical mechanical polishing. Furthermore, a need remains for alignment targets which better withstand any local erosion from occurring via dishing during chemical mechanical polishing which might otherwise erode alignment marks of an alignment target.
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Baker Daniel Claire
Drill Charles Franklin
Weling Milind Ganesh
Coleman William David
Pham Long
VLSI Technology Inc.
Wells, St. John, Roberts, Gregory & Matkins P.S.
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