Semiconductor wafer

Details Semiconductor wafer Semiconductor wafer

1992-05-27

1993-08-24

LaRoche, Eugene R.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular chip input/output means

324158R, 437 8, H01L 2940, G01R 100

Patent

active

052391914

ABSTRACT:
Upon the making of a die-sort testing for a predetermined IC pattern formed on each chip area, a plurality of sets of output pads selectively supplied with output signals are formed on the chip area and connected with a connection pattern on a dicing line area, and one testing pad is provided for the respective set of the pads. The IC patterns are tested by electrically contacting the testing pad with corresponding probe needle of probe card in a die-sort machine.

REFERENCES:
patent: 3849872 (1974-11-01), Hubacher
patent: 4721995 (1988-01-01), Tanizawa
patent: 5003374 (1991-03-01), Vokoun, III
patent: 5008614 (1991-04-01), Shreeve et al.
patent: 5032889 (1991-07-01), Murao et al.
patent: 5047711 (1991-09-01), Smith et al.
"TAB tape structure for area array tape", IBM TDB, vol. 32, No. 2, Jul. 1989, pp. 305-306.
Shultis, "Semiconductor Wafer Testing," IBM Technical Disclosure Bulletin, vol. 13, No. 7, Dec., 1970.
Bove et al., "Impedance Terminator for AC Testing Monolithic Chips," IBM Technical Disclosure Bulletin, vol. 15, No. 9, Feb., 1973.

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