Semiconductor unit

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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Details

C361S100000, C327S389000, C327S525000

Reexamination Certificate

active

07495872

ABSTRACT:
To improve the ESD protection of a circuit receiving a signal. An inverter circuit INV1is connected to ground wiring GND1for supplying power, and is connected to power supply wiring VDD1via a PMOS transistor MP5. An inverter circuit INV2is connected to ground wiring GND2and power supply wiring VDD2for supplying power, and its input node is connected to an output node of the inverter circuit INV1. Further, the ground wiring GND1and the ground wiring GND2are connected via a protection element PE0. During normal operation, the output of an inverter circuit INV3goes to an H level, the output of an inverter circuit INV4goes to an L level, and the PMOS transistor MP5is turned on. When ESD is applied, the power supply wiring VDD2is place in a floating state, the output of the inverter circuit INV4goes to an H level, the PMOS transistor MP5is turned off, and a current that occurs when EDS is applied does not flow into the inverter circuit INV2.

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