Static information storage and retrieval – Addressing – Sync/clocking
Patent
1991-11-18
1994-06-07
LaRoche, Eugene R.
Static information storage and retrieval
Addressing
Sync/clocking
365194, 307594, 307597, G11C 1300
Patent
active
053196074
ABSTRACT:
The present invention relates to a semiconductor unit including a delay circuit used for an address transition detecting circuit in a storage, wherein a change of an address is detected and, accordingly, an access address in a memory cell is altered. The present invention aims at ensuring extending an address signal even though that of a short pulse width is provided, and at outputting an address transition detection signal of a predetermined pulse width, thereby stabilizing the operation of the circuit and improving its reliability. The present invention includes a second address extending circuit having a complementary transistor circuit, a capacitor connected to the output part of the complementary transistor circuit, and a resistor serially connected between a pair of complementary transistors. A signal generating circuit for outputs an address transition detection signal in response to a non-inverted address signal, an inverted address signal, and output of the first and the second address extending circuits.
REFERENCES:
patent: 4922461 (1990-05-01), Hayakawa et al.
patent: 4926379 (1990-05-01), Yoshida
patent: 4985646 (1991-01-01), Kumagai et al.
patent: 5068553 (1991-11-01), Love
IEEE 1990 Symposium on VLSI Circuits, Jun. 9, 1990, Honolulu, USA, pp. 53-54; Sekiyama et al: "A IV Operating 256KBIT Full CMOS SRAM".
Patent Abstracts of Japan, vol. 11, No. 2 (P-532) Jan. 6, 1987 & JP-A-61 180 990.
Fujii Yasuhiro
Kodama Yukinori
Mochizuki Hirohiko
Sugiura Akira
Fujitsu Limited
Fujitsu VLSI Limited
LaRoche Eugene R.
Yoo Do Hyun
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