Semiconductor trench isolation process that utilizes...

Details Semiconductor trench isolation process that utilizes... Semiconductor trench isolation process that utilizes...

1998-12-14

2002-10-08

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S296000, C438S424000, C438S427000

Reexamination Certificate

active

06461932

ABSTRACT:

FIELD OF USE
This invention relates to semiconductor technology and, in particular, to trenched structures for isolating active regions in semiconductor devices.
BACKGROUND
For an electronic device created from a semiconductor body to operate efficiently, active regions in the semiconductor body normally have to be laterally electrically isolated from another along a surface of the body. A variety of techniques have been investigated for laterally isolating active semiconductor regions. One highly promising isolation technique is shallow trench isolation (“STI”) in which a shallow patterned trench filled with dielectric material is provided along a surface of a semiconductor body. A portion of the trench laterally surrounds each active semiconductor region. STI is advantageous because it permits the lateral device density, i.e., the density of transistors and other electronic elements present along the surface of the trench-isolated semiconductor body, to be quite high.
FIGS. 1
a
-
1
e
illustrate how STI is conventionally provided in a monocrystalline silicon semiconductor substrate
20
. A thin silicon-oxide layer
22
is provided along the upper surface of substrate
20
. See
FIG. 1
a
. A considerably thicker silicon-nitride layer
24
is deposited on oxide layer
22
.
Referring to
FIG. 1
b
, a photoresist mask
26
is formed on nitride layer
24
. The exposed material of nitride
24
and the underlying material of oxide
22
are removed as indicated in
FIG. 1
b
. Items
22
A and
24
A in
FIG. 1
b
respectively indicate the remainders of oxide
22
and nitride
24
. The exposed silicon is etched to form a shallow patterned trench
28
in substrate
20
. A dielectric layer
30
, normally consisting of oxide, is deposited on top of the structure and into trench
28
to an average thickness sufficient to fill trench
28
. See
FIG. 1
c
. The upper surface of dielectric
30
has depressions, whose depth varies from point to point, above trench
28
.
A chemical-mechanical polishing (“CMP”) technique is utilized to remove the portions of dielectric layer
30
situated above nitride
24
A. A portion of the thickness of nitride
24
A is also removed during the CMP operation.
FIG. 1
d
illustrates how the structure ideally appears after the CMP operation. Dielectric material
30
A, the remainder of dielectric
30
, fills trench
28
. Item
24
B in
FIG. 1
d
is the thinned remainder of nitride
24
A.
Remaining nitride
24
B is removed to produce the ideal trench-isolated structure shown in
FIG. 1
e
. Items
32
in
FIG. 1
e
indicate trench-isolated active regions of substrate
20
. Inasmuch as the sidewalls of trench
28
are nearly vertical, the device density can be very high. Also, the upper surface of the trench-isolated structure is relatively flat, thereby facilitating subsequent manufacturing operations.
In actual practice, it is difficult to achieve the ideal trench-isolated structure shown in
FIG. 1
e
. Various deviations from ideality arise, largely due to the inability to compensate, during the CMP operation, for variations in the lateral width of trench
28
and for variations in the spacing between portions of trench
28
. These variations arise from the pattern of the circuitry being created and are referred to here as pattern density variations.
FIGS. 2
a
and
2
b
illustrate one of the conventional difficulties caused by pattern density variations, while
FIGS. 3
a
and
3
b
illustrate another of the conventional difficulties caused by pattern density variations.
FIG. 2
a
depicts how part of the trench-isolated structure often actually appears at the stage of
FIG. 1
d
directly after the CMP operation.
FIG. 2
b
depicts how that part of the trench-isolated structure often actually appears at the stage of
FIG. 1
e
after the removal of nitride
24
B. Item
34
in
FIGS. 2
a
and
2
b
indicates a region where dielectric-filled trench
28
is relatively wide in both lateral directions and, consequently, where the depression in dielectric layer
30
is relatively deep at the stage of
FIG. 1
c
. Although the CMP operation serves to provide trench dielectric region
30
A with a moderately flat upper surface, the CMP operation often cannot fully compensate for the greater depression depth at region
34
. Consequently, trench dielectric region
30
A has a depression at region
34
. This phenomenon, commonly termed “dishing”, is disadvantageous because it degrades the upper surface planarity.
FIGS. 3
a
and
3
b
similarly respectively depict how part of the trench-isolated structure often actually appears at the stages of
FIGS. 1
d
and
1
e
. Item
36
in
FIGS. 3
a
and
3
b
indicates a region where portions of trench
28
are quite close to each other and are relatively wide in the lateral direction perpendicular to the sidewalls of region
36
. Due to this geometry at region
36
, the portion of nitride
24
A at region
36
, and the underlying portion of oxide
22
A, are often removed during the CMP operation. The underlying silicon becomes exposed during the CMP operation and is often damaged, leading to performance loss.
Various measures have been utilized to overcome the dishing and premature nitride removal problems that result from pattern density variations. These measures include (a) providing dummy active regions in areas where trench
28
would otherwise be quite wide in both lateral directions, (b) performing additional etching to remove certain parts of dielectric
30
before performing the CMP operation, and (c) implementing the CMP operation with a slurry that has high oxide-to-nitride etch selectivity. See (a) Grillaert et al, “A novel approach for the elimination of the pattern density dependence of CMP for shallow trench isolation,”
Tech. Dig
., 1998
CMP
-
MIC Conf
., Feb. 19-20, 1998, pages 313-318, (b) Withers et al, “A Wide Margin CMP and Clean Process for Shallow Trench Isolation Applications,”
Tech. Dig
., 1998
CMP
-
MIC Conf
., Feb. 19-20, 1998, pages 319-327, (c) Hosali et al, “Planarization Process and Consumable Development for Shallow Trench Isolation,”
Tech. Dig
., 1997
CMP
-
MIC Conf
., Feb. 13-14, 1997, pages 52-57, (d) Mills et al, “Raising Oxide:Nitride Selectivity to Aid in the CMP of Shallow Trench Isolation Type Applications,”
Tech. Dig
., 1997
CMP
-
MIC Conf
., Feb. 13-14, 1997, pages 179-185, and (e) Detzel et al, “Comparison of the Performance of Slurries for STI Processing,”
Tech. Dig
., 1997
CMP
-
MIC Conf
., Feb. 13-14, 1997, pages 202-206.
The preceding measures achieve varying degrees of success in compensating for pattern density variations and overcoming problems such as dishing and premature nitride removal. Unfortunately, these measures increase the process complexity considerably. Some of them require special computer algorithms for creating masks used in additional lithographic steps. The cost of STI is increased substantially. It is desirable to implement an STI process in a simple, low-cost manner in which the sensitivity to pattern density variations very small.
GENERAL DISCLOSURE OF THE INVENTION
The present invention furnishes such an implementation of the shallow trench isolation process. In the invention, a pre-smoothening technique is employed to overcome difficulties that might otherwise arise due to pattern density variations. Use of the present pre-smoothening technique results in a fully adequate trench-isolated structure without significantly increasing process complexity, and thus without significantly increasing fabrication costs.
More particularly, in accordance with the invention, a patterned trench is formed in a semiconductor body along its upper surface. The sidewalls of the trench are normally roughly vertical. A dielectric layer having a rough upper surface is provided in the trench and over the semiconductor material outside the trench.
The dielectric layer is covered with a smoothening layer whose upper surface is smoother than the rough upper surface of the dielectric layer. The smoothening layer is typically formed with material, such as spinon glass or borophosphosili

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