Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-02-27
2004-12-21
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S753000, C257S758000, C257S773000, C257S776000, C438S462000, C438S393000, C438S926000, C438S975000
Reexamination Certificate
active
06833622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to the formation of dummy structures within a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Substantially planar surfaces within a semiconductor topography may play an important role in fabricating overlying layers and structures. For example, step coverage problems may arise when a material is deposited over a surface having raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, correctly patterning layers upon a surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational “hill” or “valley” area. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a topography may increase with reductions in feature size. If a topography is nonplanar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device.
A technique that is often used to planarize or remove the elevational fluctuations in the surface of a semiconductor topography is chemical mechanical polishing “CMP.” A conventional CMP process may involve placing a semiconductor wafer face-down on a polishing pad which lies on or is attached to a table or platen. During the CMP process, the polishing pad and/or the semiconductor wafer may be set into motion as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a “slurry,” may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. Therefore, the CMP process may employ a combination of chemical stripping and mechanical polishing to form a planarized surface.
Unfortunately, a CMP process may not form a substantially planar surface across an entire semiconductor topography. For instance, the slurry may react in recessed regions, causing those regions to be excessively etched. Furthermore, the polishing rate of the CMP may be dependent upon the polish characteristics of the topography. In addition, the polishing pad, being somewhat conformal to the surface topography, may deform in response to polishing laterally adjacent layers comprising different polish properties. Therefore, while the removal rate of raised regions of the dielectric may be greater than that of the recessed regions in a typical CMP process, a significant amount of the recessed regions may, unfortunately, undergo removal. This phenomena is known as the “dishing” effect and may reduce the degree of planarization that can be achieved by the CMP process. In particular, the dishing effect may cause upper surfaces of layers and structures to curve below polished upper surfaces of adjacent structures or layers. For example, the dishing effect resulting from the fabrication of shallow trench isolation regions may be so severe that portions of the isolation regions may extend below the upper surface of the substrate. Consequently, the active regions of the device may not be adequately isolated.
In general, a topography having relatively wide regions of material may be more prone to the dishing effect than a topography having relatively narrow regions of material. As such, in an effort to reduce the dishing effect in topographies which have relatively wide regions of material, dummy structures are sometimes formed within the topography. In particular, structures which do not affect the functionality of a chip fabricated from the topography may be formed within the topography such that a substantially surface may be obtained. As a result, elevational fluctuations of the topography may be reduced and/or prevented. In general, dummy structures may be fabricated in a square pattern to simplify the layout design within an inactive region. In a preferred embodiment, the dummy structures may be arranged such that a particular plane of a topography has a substantially equal pattern density of components. In this manner, a substantially planar surface across the active and inactive regions of the topography may be obtained during a subsequent polishing process. In general, an active region of a topography may refer to the region of a topography designated for the formation of devices which are adapted to affect the functionality of a chip fabricated from the semiconductor topography. In contrast, an inactive region may refer to a region of the topography, such as an isolation structure, which does not include any devices which affect the functionality of a chip fabricated from the semiconductor topography.
In general, the number of structures that may be formed upon a topography, including those within the active and inactive regions of the topography, is typically limited by the memory space of the CAD system used to layout the chip and the computing power constraints of the system used to simulate the performance of such a chip layout. As such, in order to form active devices within the design specifications of a chip, the number of dummy structures fabricated within a topography is often limited. Such a limitation of the number of dummy structures typically results in fabricating structures with large dimensions relative to the critical dimensions of the devices within the active region of the topography. For instance, in many cases, dummy structures are fabricated with a square pattern of 7.2 &mgr;m×7.2 &mgr;m, while devices within active regions include sub-micron dimensions. Such large dummy structures, however, may still be susceptible to the dishing effect, resulting in the formation of a non-planar surface subsequent to a polishing process. In some cases, structures and layers formed above such a non-planar surface may not be formed within design specifications of the chip, causing the chip to malfunction or rendered inoperable. As a result, the reliability and production yield of devices fabricated from such a process may be undesirably low. Such a problem may become even more significant as dimensions of active devices within a topography continue to decrease with the advancement of integrated circuit technology.
As such, it would be advantageous to develop a dummy structure layout which allows a substantially planar surface to be formed across a die and/or wafer having active devices with sub-micron critical dimensions. More specifically, it would be beneficial to develop a dummy structure layout which allows a topography to have regions with substantially similar dimensions and pattern densities across the entirety of the topography without exceeding the memory space and computing power constraints of the systems used to layout the chip design and simulate the performance of the chip, respectively.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a dummy structure layout which includes a pattern of similarly sized and uniformly spaced annular dummy structures for an inactive region of a semiconductor topography. In some cases, such a dummy structure layout may be used to outline a pattern of isolation structures subsequently formed within a semiconductor substrate of the inactive region. More specifically, the dummy structure layout may be used t
Arnzen Daniel J.
Gilboa Yitzhak
Zagrebelny Andrey V.
Cypress Semiconductor Corp.
Daffer Kevin L.
Daffer McDaniel LLP
Flynn Nathan J.
Forde Remmon R.
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