Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor...
Reexamination Certificate
1997-06-18
2001-03-27
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
C257S057000, C257S059000
Reexamination Certificate
active
06207969
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor thin film formed on a substrate having an insulating surface and a semiconductor device formed by using such a semiconductor thin film. As for the semiconductor thin film, the invention particularly relates to a silicon film having crystallinity.
2. Description of the Related Art
The thin-film transistor (TFT) is typically known as the above-mentioned semiconductor device. A liquid crystal display device, an EL device, a CL device, and other devices can be constructed by using thin-film transistors.
A technique is known in which the active layer of a TFT is formed on a single crystal silicon film by using the SOI (silicon on insulator) technology. In view of the uniformity and the controllability, the thickness of the single crystal film needs to be 1 &mgr;m or more. The energy band gap (hereinafter referred to simply as Eg) of a silicon film formed by using the SOI technology is about 1.1 eV, which is approximately equal to the bulk Eg of a single crystal silicon film.
For example, consider a case where as shown in
FIG. 2A
the active layer of a TFT formed by using the SOI technology consists of conductive layers (n-type layers
201
or p-type layers
202
) and an I layer (intrinsic semiconductor layer) that constitutes the channel. In this case, the energy band is curved at the junctions to equalize the Fermi levels (indicated by broken lines in FIG.
2
A), so that an energy difference occurs between the I layer
203
and the conductive layers
201
and
202
.
In this case, since the energy difference between the I layer
203
and the conductive layers
201
or
202
is as small as about 0.5 eV, for instance, carriers are allowed to move relatively easily even when no voltage is applied to the gate electrode (no electric field state).
That is, in a graph of
FIG. 2A
in which the horizontal and vertical axes represent the gate voltage (Vg) and the source-drain current (Id), respectively, the threshold voltage of an Id-Vg characteristic
204
of an n-channel TFT is shifted to the negative side and that of an Id-Vg characteristic
205
of a p-channel TFT is shifted to the positive side, to establish a normally-on state.
A TFT whose electrical characteristic is normally on is a depletion-type TFT. That is, the depletion-type TFT has a feature that it is always in an on-state. Conversely, a TFT that is always in an off-state (normally off) is called an enhancement-type TFT. However, for the above-described reason, when it is intended to form a channel-forming region by an intrinsic semiconductor in a SOI structure, a resulting TFT is necessarily a depletion type.
Therefore, in order to form an enhancement-type TFT, the threshold voltage is controlled by implanting, into a channel-forming region
208
, an impurity for imparting p-type conductivity (for n-type conductive layers
206
) or an impurity for imparting n-type conductivity (for p-type conductive layers
207
) as shown in FIG.
2
B.
As a result, as shown in
FIG. 2B
, the energy difference between the I layer
208
and the conductive layers
206
or
207
is increased to about 0.7 eV, for instance, to form sufficiently high barriers for carrier movement. That is, since the threshold voltage of an Id-Vg characteristic
209
of an n-channel TFT is shifted to the positive side and that of an Id-Vg characteristic
210
of a p-channel TFT is shifted to the negative side, it is possible to establish a normally-off state.
As described above, when an enhancement-type TFT is formed by using the SOI technology, the prior art has some demerits as exemplified by a fact that it is necessary to implant an impurity into a channel region, which means increase of an ion implantation step.
Further, it is known that when the active layer is thick, the characteristics of a TFT are likely deteriorated by the punch-through phenomenon, the short channel effect, etc. It is reported that in order to solve this problem it is effective to decrease the thickness of the active layer. To this end, however, the thickness needs to be 500 Å or less; it is very difficult to attain such a thin active layer by the SOI technology, as described above.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above problems by forming a semiconductor thin film whose crystallinity is equivalent to that of a single crystal by a method other than the SOI technology.
Another object of the invention is to provide a technique capable of forming a high-performance semiconductor device having superior electrical characteristics by using the above semiconductor thin film.
According to one aspect of the invention, there is provided a semiconductor thin film formed on an insulating substrate, the semiconductor thin film being a silicon film having a region that can substantially be regarded as a single crystal, the silicon film having an energy band gap of 1.3 to 1.9 eV at the room temperature. The thickness of the silicon film is in a range of 100 to 850 Å.
For the reasons described below, an active layer formed by using the above semiconductor thin film has such superior performance that the problems of the SOI technology which were described in the background section can be solved.
First, a silicon film having crystallinity (crystalline silicon film) according to the invention can be formed as a thin film of 100 to 850 Å in thickness. A crystalline silicon film may be formed by crystallizing an amorphous silicon film or may directly be formed on a substrate.
Capable of forming a region that can substantially be regarded as a single crystal in a silicon thin film of 100 to 850 Å in thickness, the invention can suppress the punch-through phenomenon and the short channel effect which result from a large thickness and are problematic with the SOI technology.
The region that can substantially be regarded as a single crystal means a region having no barriers that obstruct movement of carriers, in other words, a region including substantially no grain boundaries.
An important feature of the invention is that attention is paid to the energy band gap Eg of a silicon film. The feature that Eg is in the range of 1.3 to 1.9 eV, preferably 1.4 to 1.7 eV, at the room temperature (10° to 30° C.) provides the following advantages.
As shown in
FIG. 1A
, a case is assumed in which the active layer of a TFT according to the invention consists of conductive layers (n-type layers
101
or p-type layers
102
) and a channel-forming I layer (intrinsic semiconductor layer)
103
. It is also assumed that Eg of a silicon film is 1.3 to 1.9 eV, for instance, 1.4 eV, which is different from Eg shown in the conventional case of FIG.
2
A.
In this case, an energy difference between the I layer
103
and the conductive layers
101
and
102
amounts to 0.7 eV, for instance, which is larger than that obtained when the SOI technology is used as described in the background section. Therefore, carrier movement is not effected when there is no electric field. That is, a TFT securing a normally-off state can be realized even if the channel-forming region is an I layer (intrinsic semiconductor layer). According to knowledge of the inventors, this effect can be obtained if Eg is 1.3 eV or more, preferably 1.4 eV or more.
The energy band gap Eg as used above is defined as a value obtained by determining a wavelength dependence of the effective transmittance of a silicon film by measuring an optical absorption spectrum thereof and then converting, into an energy value E, an absorption edge wavelength &lgr; at which the effective transmittance starts to decrease according to an equation E=hc/&lgr; where h is Planck's constant and c is the speed of light.
According to another aspect of the invention, there is provided a semiconductor device formed on an insulating substrate, comprising a semiconductor thin film as an active layer of the semiconductor device, the semiconductor thin film being a silicon film having a region that can substantially be regar
Fish & Richardson P.C.
Meier Stephen D.
Semiconductor Energy Laboratory Co,. Ltd.
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