Semiconductor testing device

Details Semiconductor testing device Semiconductor testing device

2003-05-07

2004-08-31

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S1540PB, C714S733000

Reexamination Certificate

active

06784686

ABSTRACT:

BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a semiconductor testing device that tests a semiconductor device based on a test pattern.
2) Description of the Related Art
Conventionally, there is known a semiconductor testing device incorporated in chip (hereinafter “semiconductor testing device”) that tests a semiconductor device disposed in the same chip by using a test pattern. Specifically, this semiconductor testing device includes a pattern generator that generates a test pattern and the semiconductor device is tested based on the test pattern generated by this pattern generator. Such a semiconductor testing device is disclosed in, for example, Japanese Patent Application Laid-open No. 8-129487 (hereinafter “patent literature 1”), on page 5, FIG. 1.
However, the conventional semiconductor testing device has the following problems.
(1) This semiconductor testing device cannot generate a test pattern that includes a subroutine, which complicates the test pattern in the end. In other words, when a jump or a loop is used in place of a subroutine, as it is not possible to use the subroutine, the test pattern itself becomes too long and complex even when a test pattern for repeating the same processing is prepared.
(2) This semiconductor testing device cannot use a subroutine and does not have a counter that measures a lapse time. Therefore, a test pattern becomes complex. When a volatile memory such as a dynamic RAM (Random Access Memory) is used in this semiconductor testing device incorporated in chip, it is necessary to rewrite data (auto refresh) at a predetermined time interval in order to avoid loss of data. However, as the semiconductor testing device cannot use a subroutine and does not have a counter that measures a lapse time, it is not possible to carry out auto refresh. Consequently, it is necessary to prepare a complex test pattern.
(3) At the time of carrying out a test by using a certain test pattern, the semiconductor testing device determines a test time (T) based on a product of a test period (t) of this test pattern and a number of times of repetition (n), that is (n×t). The semiconductor testing device cannot independently change the test period (t) or the number of times of repetition (n) by keeping the test time (T) constant. Consequently, it is complex to prepare a test pattern, change a test specification, and analyze the device.
(4) Further, the test period (t) is a function of a device operation cycle (&tgr;). Therefore, it is not possible to independently change the device operation cycle (&tgr;) by keeping the test time (T) constant. Consequently, it is not possible to carry out a performance test of the device.
Because of such problems, it is extremely important to facilitate the preparation of a test pattern, the changing of a test specification, and the device analysis respectively in a short time, by making it possible to carry out auto refresh and independent changing of a device operation cycle and a device test time. In the patent literature
1
, there is disclosed a program sequence control circuit that carries out a nesting of a subroutine with a view to increasing the speed of the circuit and simplifying the circuit, by changing a general purpose memory to a shift register. The patent literature
1
has an object of increasing the speed of the program sequence control circuit and simplifying the circuit and does not have an object of facilitating the preparation of a test pattern. Therefore, it is not possible to solve the above problems.
SUMMARY OF THE INVENTION
It is an object of this invention to at least solve the problems in the conventional technology.
The semiconductor testing device according to one aspect of the present invention is incorporated in chip in which a semiconductor device that is a target for test is incorporated. The semiconductor testing device comprises a pattern generator that generates and outputs a test pattern for testing the semiconductor device and incorporated in the chip; a stay time counting unit that starts counting a first count value that shows a stay time of a program in a first subroutine in synchronism with a predetermined first clock signal, when the pattern generator has output a test pattern that shows that the program shifts to the first subroutine, and outputs return instruction data when the first count value reaches a predetermined first value; a call waiting time counting unit that starts counting a second count value that shows a second subroutine call waiting time in synchronism with a predetermined second clock signal, and outputs call instruction data when the second count value reaches a predetermined second value; and a control unit that controls a program counter value so that the program returns from the first subroutine to a call originating routine, upon receiving the return Instruction data from the stay time counting unit and when the pattern generator has output a test pattern that shows the program returns from the first subroutine to the call originating routine, and controls the program counter value so that the program shifts to the second subroutine, upon receiving the call instruction data from the call waiting time counting unit and also when the pattern generator has output a test pattern that shows that the program shifts to the second subroutine.
The semiconductor testing device according to another aspect of the present invention is incorporated in chip in which a semiconductor device that is a target for test is incorporated. The semiconductor testing device comprises a pattern generator that generates and outputs a test pattern for testing the semiconductor device and incorporated in the chip; a stay time counting unit that starts counting a count value that shows a stay time of a program in a subroutine in synchronism with a predetermined clock signal, when the pattern generator has output a test pattern that shows that the program shifts to a subroutine, and outputs return instruction data when the first count value reaches a predetermined value; and a control unit that controls a program counter value so that the program returns from the subroutine to the call originating routine, upon receiving the return instruction data from the stay time counting unit and when the pattern generator has output a test pattern that shows that the program returns from the subroutine to the call originating routine.
The semiconductor testing device according to another aspect of the present invention is incorporated in chip in which a semiconductor device that is a target for test is incorporated. The semiconductor testing device comprises a pattern generator that generates and outputs a test pattern for testing the semiconductor device and incorporated in the chip; a call waiting time counting unit that starts counting a count value that shows a subroutine call waiting time in synchronism with a predetermined clock signal, when the pattern generator has output a test pattern that shows that the counting is started, and outputs call instruction data when the count value reaches a predetermined value; and a control unit that controls a program counter value so that a program shifts to the subroutine, upon receiving the call instruction data from the call waiting time counting unit and when the pattern generator has output a test pattern that shows the program returns to the subroutine.
These and other objects, features and advantages of the present invention are specifically set forth in or will become apparent from the following detailed descriptions of the invention when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 5931629 (1999-08-01), Rodier
patent: 6651023 (2003-11-01), Mori et al.
patent: 6714888 (2004-03-01), Mori et al.
patent: 8-129487 (1996-05-01), None

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