Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-01-21
2001-07-03
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06255844
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor testing device, and particularly to decision of PASS/FALL of a device to be tested.
FIG. 2
is a block diagram of a circuit for deciding PASS/FALL of a device to be tested in a semiconductor testing apparatus according to a prior art.
The input terminal of a driver
1
and the input terminal of a comparator
2
are connected to a device to be tested. When a testing signal is supplied to the device, the driver
1
sends an input signal to the device. When a tested signal is taken out from the device, the output from the device is supplied to the comparator
2
. The output from the comparator
2
is supplied to a PASS/FAIL deciding circuit
4
. The output from the PASS/FAIL deciding circuit
4
is supplied to an OR or AND circuit
5
. The OR or AND circuit
5
produces a FAIL output.
There are provided a plurality of drivers
1
, comparators
2
and PASS/FAIL deciding circuits
4
according to the number of terminals of the device. The output from each PASS/FAIL deciding circuit is supplied to the OR or AND circuit
5
.
A testing circuit block having such a structure is individually provided for each device to be tested.
However, when the device
3
is tested by the semiconductor testing apparatus thus structured, the following problem occurs. Namely, if the device to be tested has input/output terminals whose number exceeds that of terminals of the testing circuit block, the device cannot be tested.
In this case, as shown in
FIG. 3
, if there is an unused testing circuit block (testing circuit block corresponding to DUTn), it can be used for testing. However, two testing circuit blocks are used to test a single device so that the number of the devices
3
to be simultaneously tested must be reduced to ½.
SUMMARY OF THE INVENTION
The present invention has been accomplished in order to solve the above problem, and intends to provide a semiconductor testing apparatus which can minimize the reduction in the number of the devices to be simultaneously tested even if the number of the input/output terminals of the device to be tested exceeds that of the terminals of the testing circuit block in the semiconductor testing apparatus.
The invention defined in Aspect
1
is a semiconductor testing apparatus capable of simultaneously testing a plurality of devices to be tested to which a plurality of testing circuit blocks are allotted, respectively, comprising an arithmetic circuit for receiving all outputs from the plurality of testing circuit blocks to compute the decision results from the plurality of devices.
The invention defined in Aspect
2
is a semiconductor testing apparatus according to aspect
1
, wherein the arithmetic circuit classifies outputs from the plurality of testing circuit blocks according to the devices to be tested and takes an OR and AND thereof.
The invention defined in Aspect
3
is a semiconductor testing apparatus according to aspect
1
or
2
, wherein the testing circuit block comprises: a comparator for comparing an output from the device to be tested with a reference value, and a PASS/FAIL deciding circuit for deciding PASS/FAIL of the output from the device to be tested on the basis of the comparison result from the comparator.
REFERENCES:
patent: 4928278 (1990-05-01), Otsuji et al.
patent: 5390129 (1995-02-01), Rhodes
patent: 5579251 (1996-11-01), Sato
patent: 5794175 (1998-08-01), Conner
Ando Electric Co. Ltd.
Fish & Richardson P.C.
Karlsen Ernest
Tang Minh
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