Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1996-07-11
1999-10-19
Ballato, Josie
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
439179, G01R 3102
Patent
active
059695340
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed both to an apparatus for the reversible contacting of a semiconductor circuit level to assist in performing a function test and to a method for testing semiconductor circuit levels upon employment of such an apparatus.
2. Description of the Prior Art
Semiconductor circuits are currently manufactured using planar circuit technology. The complexity that can be achieved on a single chip is limited by the chip's size and structural fineness. Given conventional technology, the performance capability of a system composed of a plurality of semiconductor chips connected to one another is essentially limited by: the number of possible connections between individual chip's terminal contacts (pads); the low speed of the signal transmission via such connections between various chips; the limited speed through highly-branched interconnects on complex chips; and the high power consumption of interface circuits.
These limitations which are associated with planar technology can be overcome with three-dimensional interconnection techniques. The arrangement of function levels, one above another, allow a parallel communication between components with little outlay of electrically-conductive connections in a single level (also referred to as "cubically-integrated") Further, speed-limiting interchip connections may be avoided. Such a cubically-integrated semiconductor chip may still be accommodated in a single housing despite its enhanced functionality.
To avoid unnecessary losses in the yield of functional chips, only those circuit levels which have been tested and found to be fully functional are placed above one another and contacted. Such arrangement is unproblematic as long as the circuit levels are "self-sufficient," i.e., independently-functioning circuits. With self-sufficient circuits, it is possible to test them after they are connected to a wafer, yet before they are passivated, separated and mounted in housings. When, however, a circuit level only functions when interacting with its vertically-neighboring circuit levels, the testing of such circuit level is only possible after the irreversible assembly of the various other circuit levels. This process should be avoided, however, because it drastically reduces the obtainable yield.
For testing purposes, the circuits are usually contacted by placing fine test probes onto the bond pads. However, the pads have significantly larger dimensions than the connection contacts of the circuit levels that are provided for the cubic integration. In addition, the number of contacts is significantly great (about 10,000 through 100,000). As a result of both the fine dimensions and the great number of contact locations, the use of standard test probes is precluded.
Another testing method employs electron-optical methods. This method, however, requires self-sufficient circuit levels, a prerequisite that, as already mentioned, is not met with cubic integration. Further, the voltage supply may not be assured, particularly given insulated circuit levels. In sum, these testing methods cannot be employed for testing individual semiconductor circuit levels that are provided for cubic integration.
An object of the present invention, therefore, is to provide semiconductor circuit levels, especially those having non-self-sufficient circuits, which can be subjected to a function test before their cubic integration.
SUMMARY OF THE INVENTION
This object is achieved in an apparatus for the reversible contacting of a semiconductor circuit level wherein the apparatus includes a testing head having an essentially planar upper side and a plurality of recesses arranged in a test side at locations which provide for contact with the semiconductor circuit level. The apparatus further includes a plurality of test points formed by liquid contacts located in the plurality of recesses in the test side of the testing head such that a free surface of the liquid contacts projects beyond the test side.
The object is furth
REFERENCES:
patent: 2947939 (1960-08-01), Harwig
patent: 4409546 (1983-10-01), Shulman
patent: 4521730 (1985-06-01), Shulman
patent: 4585991 (1986-04-01), Reid et al.
patent: 4833402 (1989-05-01), Boegh-Petersen
patent: 5258648 (1993-11-01), Lin
patent: 5358417 (1994-10-01), Schmedding
patent: 5585736 (1996-12-01), Hshieh et al.
IBM Technical Disclosure Bulletin, "Burn-in/In Situ Testing of Computer Chips", vol. 36, No. 03, Mar. 1993, pp. 229-231.
Hubner Holger
Klose Helmut
Koppe Siegmar
Weber Werner
Ballato Josie
Kobert Russell M.
Siemens Aktiengesellschaft
LandOfFree
Semiconductor testing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor testing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor testing apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2060705