Semiconductor tester synchronized with external clock

Details Semiconductor tester synchronized with external clock Semiconductor tester synchronized with external clock

1997-04-25

1999-03-23

Nguyen, Vinh P.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

3241581, G01R 2302

Patent

active

058865365

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to a synchronization circuit, to be used in a semiconductor tester to receive an external clock signal, which removes jitters of the clock signal and synchronizes an internal clock signal of the semiconductor tester with the external clock signal.


BACKGROUND ART

An example of the conventional technology is represented in FIG. 3. In a semiconductor tester, an operation clock signal is generated inside the test system. Test patterns are generated in synchronism with the clock signal and applied to a semiconductor device under test. The resultant output signals from the device under test are compared with expected pattern. In such an arrangement, a problem of producing jitters does not occur since all the operation in the system is synchronized with the internal clock signal. On the other hand, there is a semiconductor device which generates a clock signal by itself. In such a case, a method may be used for utilizing the clock signal from the device itself to operate the semiconductor tester. In this method, the internal clock of the semiconductor tester has to be synchronized with the clock signal from the device under test. However, the problem of jitters will occur between the two clocks as shown in FIG. 4 since the two clocks are completely out of synchronization.
Therefore, it is an object of the present invention to solve this problem and to provide a semiconductor tester circuit which will not generate jitters when using an external clock signal.


DISCLOSURE OF THE INVENTION

According to the first embodiment of this invention, a divider is provided which receives an external clock signal generated by a semiconductor device under test at an input terminal and divides the clock signal by 1/N. A phase detector is provided which receives the output of the divider and an output of another divider. A loop filter is provided which takes the output of phase detector as an input signal. A voltage controlled oscillator (hereinafter "VCO") is provided which receives the output of the loop filter as an input. The output signal of the VCO is provided to an input of a test rate generator which provides the output of the VCO to various circuits in the semiconductor tester. A divider is provided which receives the output of the test rate generator as an input signal and divides the input signal by 1/N. The output of the divider is taken as the input of the phase detector as noted above.
According to the second embodiment of the present invention, a test signal frequency generator is provided which can set a test signal frequency in high resolution, such as 1 Hz increment. A divider is provided which receives a clock signal generated by the test signal frequency generator at an input terminal and divides the received clock signal by 1/N. A phase detector is provided which receives the output of the divider and an output of another divider. A loop filter is provided which takes the output of phase detector as an input signal. A VCO is provided which receives the output of the loop filter as an input. The output signal of the VCO is provided to an input of a test rate generator which provides the output of the VCO to various circuits in the semiconductor tester. A divider is provided which receives the output of the test rate generator as an input signal and divides the input signal by 1/N. The output of the divider is taken as the input of the phase detector as noted above.
Because of the arrangement of the embodiments of the present invention described above, a phase Locked Loop (PLL) is formed by interactions of the divider A, the phase detector, the loop filter, the VCO and the divider B. Thus, the clock signal received asynchronously can be converted to an operation clock having high stability. In other words, the present invention provides an operation clock which does not have jitter components.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the first embodiment of the present invention.
FIG. 2 is a block diagram showing the second embodiment of

REFERENCES:
patent: 5295079 (1994-03-01), Wong et al.
patent: 5511126 (1996-04-01), Westwick

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