Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-07-15
2001-08-14
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S755090
Reexamination Certificate
active
06275057
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor test system having a high repetition rate and small jitter clock generator, and more particularly, to a semiconductor test system which is able to apply high frequency and low jitter clock signals to an IC device to evaluate the performance of the IC device.
BACKGROUND OF THE INVENTION
In testing a semiconductor IC device, a semiconductor test system applies a test pattern signal to a device under test (DUT) and the resultant output signal of the DUT is compared with an expected value signal. An example of basic structure of a semiconductor test system is shown in FIG.
4
. Based on a test program, a test processor (TP)
1
controls an overall operation of the test system by sending control signals to each unit of the test system through a tester bus. A pattern generator (PG)
2
generates a test pattern to be supplied to a device under test (DUT)
9
and an expected data pattern to be supplied to a logic comparator
7
. A timing generator (TG)
3
generates timing pulses to be supplied to a wave formatter (WF)
4
, the logic comparator and other functional blocks to synchronize various timings in the test system.
The test pattern from the pattern generator
2
is formed to a specified waveform such as an RZ (return to zero), NRZ (non-return to zero), or EOR (exclusive OR) waveform by the wave formatter
4
. The test pattern from the wave formatter
4
is then applied to the DUT
9
through a driver
5
which defined an amplitude and slew rate of the test pattern. An output signal of the DUT
9
produced in response to the test pattern is provided to the logic comparator
7
through an analog comparator
6
. The logic comparator
7
compares the output signal with the expected data pattern from the pattern generator
2
. If the output signal mismatches the expected data, the test system determines that the DUT
9
has failed in the test. The fail information is stored in a fail memory (FM)
8
in the test system along with other information, such as address data, from the pattern generator
2
to be used in a failure analysis process following the test.
Semiconductor IC devices are ever increasing in the density, speed and functionality. Some of the recent LSI (large scale integrated circuit) circuits include many complicated sequential circuits which form combinational circuits and memory circuits therein. One of the methods of testing such a complicated LSI circuit is an LSSD (Level Sensitive Scan Design) having a scan architecture in which memory elements in the LSI circuit are accessed through shift register stages. In this architecture, a large number of memory elements can be tested through a small number of external pins by scanning the series connected shift register stages. To fully evaluate such an LSI circuit, a semiconductor test system must provided high frequency and low jitter clock signals to the LSI circuit under test.
An architecture of semiconductor test system is also changing with the development of LSI devices to be tested. Traditionally, an architecture called a shared resource tester is widely used, while modernly, an architecture called a per-pin tester is developed for a more complicated and large scale LSI circuit. Here, the shared resource tester is a tester architecture which includes a plurality of identical resources such as timing generators, wave formatters, reference voltages, etc. wherein the number of such identical resources is smaller than the number of test pins (channels) of the semiconductor test system. Thus, the common resources must be shared among the test pins.
The per-pin tester, on the other hand, includes the same number of identical resources as the number of test pins so that test parameters in each test pin can be set independently from the other test pins. Although requiring more expensive and larger size hardware, the per-pin tester is suitable for testing a complicated LSI circuit, since test patterns and timings can be more freely produced than the shared resource tester.
In the per-pin tester, a frame processor is provided in each test pin. The frame processor performs the functions of the timing generator
3
, wave formatter
4
and logic comparator
7
in the conventional shared resource tester of FIG.
4
. The frame processor produces a test waveform which is formed of a plurality of single frames. Usually, a time length of a single frame is the same as a time period of a reference clock used in the test system.
In a semiconductor test system, the maximum operational speed of inner circuits and components is designed to accommodate the frequency of a reference clock so that all of the test system can be synchronized with the reference clock. For example, when the reference clock frequency is 100 MHz, the maximum operational speed of the frame processor must be greater than 100 MHz. In the case where the frequency of the reference clock is 200 MHz, the frame processor or other circuits must be able to operate at 200 MHz or higher. The reference clock must also be provided to an LSI device under test as test signals.
Because of the increase in the operational speed of the recent semiconductor devices, a semiconductor tester is not always able to meet the requirements of generating the maximum clock speed. For example, some of the most recent LSI devices require reference clock frequencies of 1,200 MHz to be fully tested, which is usually not possible for a large semiconductor test system. To overcome this problem, a semiconductor test system employs an interleave method in which a plurality of lower speed circuits are provided in a parallel fashion and interleaved (multiplexed) in a series fashion to achieve a higher speed operation.
FIG. 5
is a block diagram showing an example of clock generator for providing a clock signal to an LSI device under test by means of the interleave method. A reference clock generator
11
provides a clock signal to a plurality of frame processors
12
1
-
12
n
in a parallel fashion. The outputs of the frame processors
12
1
-
12
n
are provided to a multiplexer
13
whose output is connected to a driver
14
. The driver
14
provides the clock signal to a clock terminal
10
of the device under test
9
through a test pin
15
.
The clock signals from the frame processors
12
1
-
12
n
are phase-shifted and sequentially combined by the multiplexer
13
to produce a series clock signal. Thus, the overall repetition rate of the clock signal at the output of the multiplexer
13
is multiplied by the number of frame processors incorporated. For example, when the reference clock frequency is 100 MHz, and two frame processors
12
1
and
12
2
are used in parallel, the reference clock of one frame processor is delayed by 5 ns (nanosecond) from the other. Then, the two clock signals are combined into a series clock signal, which results in 200 MHz in frequency. By increasing the number of frame processors
12
, a higher frequency of the clock signal can be obtained accordingly.
However, as shown in
FIG. 6
, the clock signal generated by the reference clock generator
11
includes jitter or fluctuations. Such jitter remains the same when the plurality of clock signals are multiplexed and combined into a high frequency clock signal in the interleave method. Thus, the ratio of jitter versus time period of the clock signal increases with the increase of the clock signal frequency, which makes it impossible to test a semiconductor device with high timing resolution.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a semiconductor test system having a clock generator which is able to apply high frequency and low jitter clock signals to an IC device under test to evaluate the performance thereof.
It is another object of the present invention to provide a semiconductor test system which is capable of generating a specified number of clock pulses with low jitter to a semiconductor device to be tested.
It is a further object of the present invention to provide means for generating high frequency and lo
Advantest Corp
Brown Glenn W.
Muramatsu & Associates
Nguyen Jimmy
LandOfFree
Semiconductor test system having high frequency and low... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor test system having high frequency and low..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor test system having high frequency and low... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2436397