Data processing: measuring – calibrating – or testing – Measurement system – Statistical measurement
Reexamination Certificate
2002-02-13
2003-12-30
Bui, Bryan (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Statistical measurement
C702S118000
Reexamination Certificate
active
06671653
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor test system, and a monitor apparatus and a filter device incorporated with the semiconductor test system for individually monitoring information on certain components used in the semiconductor test system, such as numbers of operation of relays, and for effectively maintaining such components to easily achieve high reliability of the semiconductor test system.
BACKGROUND ART
An example of the structure and operation of the semiconductor test system in the conventional technology will be briefly explained with reference to
FIGS. 5-7
.
As shown in
FIG. 7
, the semiconductor test system is comprised of an engineering work station (EWS)
10
, a main frame
20
, a test head
30
, a performance board
80
, and an IC socket
90
.
The work station
10
is an input and output means for man/machine interfacing between the semiconductor test system and a user.
The main frame
20
includes various power sources, a tester processor, and test units for corresponding test pins (test channels) of the semiconductor test system.
The test head
30
includes a large number of printed circuit boards forming pin electronics
40
which are electronic circuits establishing a large number of test channels (test pins) noted above.
The performance board
80
is a printed circuit board designed for a specific semiconductor device to be tested (hereafter “DUT”). The performance board
80
is interchangeable. The IC socket
90
corresponding to the DUT is mounted on the performance board
80
.
The IC socket
90
is a socket having a number of pins, size and shape corresponding to the semiconductor device to be tested.
In the semiconductor test system configured as described above, a device test proceeds as follows with reference to the block diagram of FIG.
5
.
Here, in order to simplify the explanation, the diagram of
FIG. 5
shows only one test channel, i.e., one pin electronics
40
. However, it should be noted that a large number of such test channels are established in an actual test system. Thus, in the case where the test system has 512 test channels, 512 pin electronics
40
each being configured as shown in
FIG. 5
are installed in the test system.
When conducting a DC parametric test, for example, by supplying a voltage and measuring a resultant current, a relay S
12
is turned off (break) and a relay S
11
is turned on (make). A direct current (DC) test unit
8
generates a test voltage which is applied to an intended pin of the DUT
91
, and a current flowing through the pin is measured.
When conducting a functional test for each I/O pin of the DUT
91
, the functional test is performed in the manner described in the following.
The pattern generator
5
generates a logic data, which is synchronized with the reference clock signal generated by the timing generator
4
.
The wave formatter
6
generates a test pattern based on the logic data from the pattern generator
5
and the reference clock signal from the timing generator
4
.
In the pin electronics
40
, relays S
11
and S
13
are turned off and relay S
12
is turned on, and the test pattern is amplified to a predetermined voltage level (VIH/VIL) by a driver D
11
and is supplied to the corresponding pin of DUT
91
.
The response output signal from the DUT
91
is terminated by a resistor R
1
while the relay S
11
is turned off and the relay S
13
is turned on. Also, the relay S
12
is turned on so that the output signal is converted to a logic signal by a comparator C
11
and is output therefrom.
By the logic comparator
7
, the resultant logic signal is compared with an expected value produced by the pattern generator
5
at the timing of a strobe signal from the timing generator
4
. The logic comparator
7
determines whether the output signal of DUT
91
matches the expected value, i.e., pass or fail of the test on the DUT
91
.
An example of relay control in the pin electronics
40
and the operation of functional blocks in the test system will be explained with reference to FIG.
6
.
Here, it is assumed that relays S
11
-S
1
n
represent relays corresponding to all of the test channels of the pin electronics in the semiconductor test system.
As shown in
FIG. 6
, the semiconductor test system includes the functional blocks, such as a tester processor
2
for overall control of the test system, a control unit
3
, the timing generator
4
, the pattern generator
5
, the wave formatter
6
, the logic comparator
7
, and the DC test unit
8
. The above noted functional blocks are connected and controlled through a tester bus
200
.
The tester bus
200
is structured by lines for 8-bit address and data, for example, and control signals including clocks. The tester bus
200
serially transfers 32-bit address and 32-bit data by dividing the data into each 8-bit data.
The control unit
3
sends control signals to the test head
100
. The control signals include supply voltage levels (VIH/VIL) of the drivers
11
in the pin electronics
40
and control data to a relay control circuit
31
.
Although the block diagram of
FIG. 6
illustrates each of the control unit
3
and other functional blocks as one unit, such unit and blocks may be combined together or a plurality of same units and blocks may be incorporated in the test system.
The relay control circuit
31
generates control signals for determining which relays of which channels should be controlled.
As an example, the relays S
11
-S
1
n
are reed relays which turn on (make) or turn off (brake) by controlling the on/off of the electromagnetic coils through drivers D
21
-D
2
n.
When three relays are used per channel for a test system of 512 test channels, then the total number of relays will be 1,536.
Since the actual number of relays used is about 3-8 per test channel depending on the type of the pin electronics, the overall number of relays becomes very large.
The relays S
1
-S
1
n
will be turned on/off in a dry condition where contact points are not flowing current, or will be turned on/off in a wet condition where the contact points are flowing current.
Typically, for attaining a longer life span, the relays S
11
-S
1
n
are turned on/off in the dry condition, however, they will sometimes be turned on/off in the wet condition depending on the test conditions and purposes.
The description will be made in the following regarding the maintenance of a semiconductor test system.
A semiconductor test system uses a large number of components having relatively short life spans, such as reed relays and motors, and capacitors whose performances will change with lapse of time.
Therefore, information regarding the number of operations of the relays is accumulated by a counter
1
which counts the number of ON/OFF control signals.
However, in practice, it is difficult to find an appropriate time to exchange the relays since the number of on/off operations of a relay varies depending on the test program. Further, there is a significant difference in the life span of the relays between the on/off operations in the dry condition and wet condition. Further, the total number of relays and other short-life components is large, it requires a complicated procedure to acquire sufficient information regarding the status of such components.
DISCLOSURE OF THE INVENTION
As described in the foregoing, in the conventional semiconductor test system, it is difficult to fully perform the maintenance work because it is not possible to obtain individual information regarding each short life component and time changing component.
Therefore, the present invention was made in view of such problems, and it is an object of the present invention to provide a semiconductor test system and an associated monitor apparatus which is capable of monitoring the test histories, for example, numbers of operations of mechanical components such as relays.
In searching the monitor information such as a test history through the tester bus, a data search and retrieve operation takes a long time if it is done by a traditional software process because it requires a
Ihata Tsuyohiro
Nakamura Masafumi
Sato Atsushi
Advantest Corp.
Bui Bryan
Muramatsu & Associates
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