Data processing: software development – installation – and managem – Software program development tool – Testing or debugging
Reexamination Certificate
2000-08-15
2004-04-20
Das, Chameli Chaudhuri (Department: 2122)
Data processing: software development, installation, and managem
Software program development tool
Testing or debugging
C717S126000, C717S138000, C703S014000, C703S019000, C709S217000, C709S223000, C714S025000, C714S018000, C714S038110
Reexamination Certificate
active
06725449
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor test program debugging apparatus which simulates an operation of a semiconductor test apparatus to verify a test program, and in particular to the semiconductor test program debugging apparatus for facilitating verification of a test program for a packet transfer memory device.
Semiconductor test apparatuses have been known which is used for DC tests and functional tests of various semiconductor devices such as logic ICs and semiconductor memory before shipment of them. The test conducted by means of the semiconductor test apparatuses are broadly classified as a functional test and a DC test. A functional test is conducted by providing a predetermined test pattern signal to a device under test (hereinafter referred to “DUT”) to determine whether the DUT performs a predetermined operation in response to the test pattern. A DC test is conducted for determining whether the DC characteristics of terminals of a DUT meet predetermined characteristics. The DC tests include, for example, a voltage-application current-measurement test for determining whether a predetermined current is output from a terminal when a known voltage is applied to a DUT and a current-application voltage-measurement test for determining whether a predetermined voltage appears at a terminal when a known current is fed to or took from a DUT. Also in the functional tests, it is often the case where a voltage and currents applied to a DUT are changed for testing: for example, a voltage lower than a predetermined voltage is set as a high-level voltage (for example, 4 volts, which is lower than normal 5 volts, is set as the high-level voltage) or a voltage higher than a predetermined voltage is set as low-level voltage (for example, 0.5 volts, which is higher than normal 0 volts is set as the low-level voltage).
Because the details of a functional or DC test, such as what test items are conducted under what conditions, are pre-specified by a semiconductor test program, various tests can be conducted on a DUT by executing the semiconductor test program. The semiconductor test program must control wide variety of operations such as test item and condition setting, execution of a test, and judgement of the test result, and therefore consists of an enormous number of steps. If the type or logic of a DUT is changed, various changes must be made to the semiconductor test program accordingly. When a semiconductor test program is newly written or modified, the program must be evaluated to see if the program itself operates properly or not.
Conventionally a semiconductor test program is evaluated by executing the program with the use of real semiconductor test apparatuses. However, it is not desirable to use the real semiconductor test apparatuses to evaluate to see if the semiconductor test program operates properly or not because the number of installed semiconductor test apparatuses is small due to their high price and the production line of the semiconductor testing is halted by the evaluation. To address this problem, in these days, rather than using a real semiconductor test apparatus for the evaluation of a semiconductor test program, the operation of the semiconductor test apparatus is simulated by means of a general purpose computer such as a workstation to determine whether a semiconductor test program operates or not.
However, when a semiconductor test program for a new type of device called a packet transfer memory device is verified by configuring and using a virtual semiconductor test apparatus as heretofore, problems arise as described bellow. Unlike conventional memory devices, the packet transfer memory device does not have predetermined address pins or data pins, instead, it extracts an address and data based on packet data inputted to a predetermined number of pins and reads/writes data based on the extracted address and data.
The packet transfer memory device therefore cannot be tested by simply applying data generated according to a semiconductor test program to the pins of the device like the address pins and data pins of conventional memory devices. A user must write a semiconductor test program while taking care to ensure that data is generated according to the configuration of packet data specific to the packet transfer memory device. In addition, it is required to be verified that data generated by the written semiconductor test program is corresponding to the packet data specific to the packet transfer memory device. Heretofore, this verification is manually performed by the user printing or displaying on a CRT the data output by the execution of the semiconductor test program.
SUMMARY OF THE INVENTION
The present invention is made in view of the above-mentioned problems and it is an object of the present invention to provide a semiconductor test program debugging apparatus which allows a semiconductor test program for a semiconductor device, such as a packet transfer memory device which operates based on packet data to be easily debugged.
The semiconductor test program debugging apparatus of the present invention comprises tester simulation unit for simulating the operation of a semiconductor test apparatus by generating a test signal in a simulative manner based on a test program provided for a packet transfer memory device, data supply unit for supplying data concerning a packet input to and output from the packet transfer memory device, and packet extraction and display unit for, based on the data supplied by the data supply unit, extracting a part corresponding to the packet from the test signal generated by the tester simulation unit and displaying the content thereof.
The tester simulation unit runs the test program to be debugged under the operating system of a general-purpose computer and constitutes a semiconductor test apparatus in a simulative manner. The data supply unit supplies, as the data concerning a packet, information about a packet data configuration specific to a packet transfer memory device and pins through which the packet is input or output. The packet extraction and display unit extracts, based on data concerning the packet, a part corresponding to the packet from data which is a test signal output from the test simulation unit and is input/output through a predetermined pin, and displays the detailed configuration of the packet which correspond to the part. The user can debug the semiconductor test program by verifying whether the displayed details of the packet match desired details or not.
The data supply unit above-mentioned preferably supplies information about predefined pin conditions of the packet transfer memory device, a pin group making up the packet, the configuration of the packet, and the starting position of the packet as the data concerning to the packet. This data is prescribed data concerning the packet to be supplied by the data supply unit. By using this detailed data, the part corresponding to the packet can be easily extracted from a test signal generated by the tester simulation unit.
The data supply unit above-mentioned preferably accepts various inputs through a graphical user interface (GUI) screen to generate the data concerning the packet. Because the user can input information such as pin conditions by simply selecting or inputting appropriate information through a predetermined definition screen, the labor for inputting data about the packet can be reduced.
The packet extraction and display unit above-mentioned preferably displays the part corresponding to the packet in a timing chart image using step values of the simulation operation by the tester simulation unit for the time axis. This timing chart image specifies how the packet extraction and display unit displays packets. This allows the user to easily know the position of a packet in data sequentially input to and output from the packet transfer memory device.
The packet extraction and display unit above-mentioned preferably displays output values during each cycle for each pin in a way that components contai
Maeda Hironori
Maeda Yoshinori
Oda Tadashi
Advantest Corporation
Das Chameli Chaudhuri
Dellett & Walters
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