Semiconductor test management system and method

Details Semiconductor test management system and method Semiconductor test management system and method

2006-12-26

2006-12-26

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C700S121000

Reexamination Certificate

active

07155361

ABSTRACT:
A system and method for semiconductor test management. A second computer receives a scrap rule from a first computer, acquires an initial scrap threshold corresponding to the scrap rule, stores the scrap rule as a SBC/SBL (Statistic BIN Control/Statistic BIN Limit) rule when a scrap condition therein is less or equally restrictive than the initial scrap threshold, acquires a CP (Circuit Probing) test result for a wafer or wafer lot and generates an advisory report for the wafer or wafer lot by carrying the CP test result into the stored SBC/SBL rules.

REFERENCES:
patent: 6041270 (2000-03-01), Steffan et al.
patent: 6055463 (2000-04-01), Cheong et al.
patent: 6319737 (2001-11-01), Putnam et al.

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