Semiconductor system-in-a-package containing micro-layered...

Details Semiconductor system-in-a-package containing micro-layered... Semiconductor system-in-a-package containing micro-layered...

2011-04-12

2011-04-12

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S690000, C257S724000, C257S773000, C257S776000, C257S780000, C257S786000, C257SE25006, C257SE25013, C257SE25021, C257SE25027, C257SE23015, C257SE23020, C257SE23085

Reexamination Certificate

active

07923847

ABSTRACT:
Semiconductor packages that contain a system-in-a-package and methods for making such packages are described. The semiconductor packages contain a first semiconductor die resting on a middle of a land pad array, a second die disposed over the first die and resting on routing leads that are connected to the land pad array, a third die resting on the backside of the second die and connected to the land pad array by wire bonds, and a passive device and/or a discrete device resting on device pads. The packages also contain thermal pads which operate as a heat sink. The land pad array is formed from etching the leadframe. The semiconductor packages have a full land pad array with a thin package size while having a system-in-a-package design. Other embodiments are also described.

REFERENCES:
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patent: 6734555 (2004-05-01), Boireau
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patent: 7163842 (2007-01-01), Karnezos
patent: 7446398 (2008-11-01), Niu et al.
patent: 7449364 (2008-11-01), Lyne
patent: 7855448 (2010-12-01), Seaman et al.
U.S. Appl. No. 12/199,065, filed Aug. 27, 2008.
U.S. Appl. No. 12/332,207, filed Dec. 10, 2008.

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