Semiconductor synchronous pipeline memory having data amplifiers

Static information storage and retrieval – Addressing – Sync/clocking

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365205, 365 63, G11C 800

Patent

active

060916621

ABSTRACT:
A semiconductor synchronous pipeline dynamic random access memory device has a first read data amplifier and plural second read data amplifiers connected through a read/write data bus to the first read data amplifier, and read-out data bits are alternately supplied to the plural second read data amplifiers so that the read-out data bit is never destroyed by the next read-out data bit.

REFERENCES:
patent: 5550784 (1996-08-01), Takai
patent: 5729500 (1998-03-01), Shinozaki
patent: 5859793 (1999-01-01), Satani et al.
patent: 5895482 (1999-04-01), Toda

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