Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-07-18
2002-06-25
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
C438S007000, C257S048000
Reexamination Certificate
active
06410354
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor substrate test devices and methods, and more particularly to a semiconductor substrate test device and method for testing a semiconductor substrate by placing a plurality of terminals formed on the semiconductor substrate in contact with contact electrodes formed on a contactor.
In recent years, finer pitches in semiconductor devices represented by large-scale ICs have caused circuits to have higher density and terminals to be increased in number and smaller in size.
Such higher density of semiconductor devices is essential in electronic devices employing the semiconductor devices, for instance, small portable devices such as a telephone, a mobile personal computer, and a video-integrated camera, and high-performance computers required to have high-speed operation reliability.
Therefore, a demand has been rapidly increased for shipping the semiconductor devices in the form of a KGD (Known Good Die), that is, in an unpackaged chip state with guarantees on their functions, or in the form of a CSP (Chip size package) that is a small-size package having the same outer dimensions as those of an LSI chip.
Further, in the light of increasing the efficiency of the tests of the semiconductor devices, there has been growing necessity for conducting all reliability tests on semiconductor chips in a wafer state before the wafer is cut into the individual semiconductor chips instead of testing each individual semiconductor chip separated from the wafer. Hereinafter, a test conducted on semiconductor chips in a wafer state is referred to as a wafer-level test.
2. Description of the Related Art
A conventional wafer-level test is conducted by electrically connecting a plurality of semiconductor chips formed on a wafer with a contactor by placing a plurality of terminals formed on the semiconductor chips in contact with contact electrodes formed on the contactor.
This wafer-level test allows a reliability test to be conducted without cutting the wafer into individual semiconductor chips, thus increasing the handling efficiency of the test. That is, the individual semiconductor chips obtained by dicing vary in size so as to be prevented from being handled by the same handler, while the wafer is handled easily in the wafer-level test since the wafer is standardized in size and tested directly by the wafer-level test.
Further, the wafer-level test provides information on the acceptability of the semiconductor chips, which information can be managed as a wafer map. Therefore, the wafer-level test allows analysis of which semiconductor chip on the wafer has what type of deficiency, and can be easily compared with a preliminary test (PT), thus increasing the reliability of a test process.
Moreover, in the case of a recently developed wafer-level CSP, semiconductor chips are processed in a wafer state all through to the end of a CSP packaging process in a production process. If a test on the semiconductor chips in the wafer state is realized and added to this, the semiconductor chips can be handled in the form of a wafer all through the processes of a wafer process, packaging, and test, thus making the production process more efficient.
However, the above-described wafer-level test includes the following disadvantage due to the above-described increase in the number of terminals and decrease in the size of a terminal shape.
That is, the number of terminals formed on a wafer sums up to a very large number, that is, 20,000 to 100,000, in the case of an eight-inch wafer, for instance. In order to place these numerous terminals in secure contact with the contact electrodes of the contactor of a test device, supposing that a contact force of approximately 98 mN per terminal is required, a contact force of approximately 2,000 to 10,000 N is required for the entire wafer.
If the wafer is to be placed in contact with the contactor of the test device by such a large contact force, the contactor may give way to the load to be distorted and deformed to such an extent that the contactor may finally be broken. Further, the wafer as well as the contactor may be damaged.
In this case, the contactor may be reinforced by a plate. However, this method cannot altogether prevent the deformation of the contactor although effective in reducing the deformation to some extent, and this residual deformation of the contactor causes poor connections between the contactor and the terminals of semiconductor devices formed minutely with high density. Further, the reinforcement of the contactor by the plate adds to the weight of the contactor, thus making it difficult to handle the contactor, for instance, in carrying it.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor substrate test device and method in which the above-described disadvantage is eliminated.
A more specific object of the present invention is to provide a semiconductor substrate test device and method for conducting a test on each of semiconductor devices formed on a semiconductor substrate, without distorting, deforming, and breaking a contactor, by placing terminals formed on the semiconductor devices in contact with terminals formed on the contactor.
The above objects of the present invention are achieved by a semiconductor substrate test device including a contactor having contact electrodes formed on a first face thereof, the contact electrodes being connected with terminals formed on a first face of a semiconductor substrate, and a drag supply part supplying a drag to prevent a deformation of the contactor, the deformation being caused by a contact force generated when the contact electrodes are placed in contact with the terminals.
According to the above-described semiconductor substrate test device, the contact force and the drag applied to the sides of the contactor are balanced with each other, thus preventing the distortion, deformation, and breakage of the contactor.
The above objects of the present invention are also achieved by a semiconductor substrate test device including a contactor having contact electrodes formed thereon, the contact electrodes being connected with terminals formed on a semiconductor substrate, a sensor detecting a deformation of said contactor, the deformation being caused by a contact force generated when the contact electrodes are placed in contact with the terminals, and a deformation control part generating a drag to eliminate the deformation.
According to the above-described semiconductor substrate test device, an appropriate drag for eliminating the deformation of the contactor can be supplied with accuracy.
The above objects of the present invention are also achieved by a method of testing a semiconductor substrate including the steps of (a) placing contact electrodes formed on a contactor in contact with terminals formed on the semiconductor substrate, and (b) providing a contact force to place the contact electrodes in contact with the terminals and a drag to prevent a deformation of the contactor caused by the contact force.
According to the above-described method, the contact force and the drag applied to the sides of the contactor are balanced with each other, thus preventing the distortion, deformation, and breakage of the contactor.
The above objects of the present invention are further achieved by a method of testing a semiconductor substrate by placing contact electrodes formed on a contactor in contact with terminals formed on the semiconductor substrate, which method includes the steps of (a) detecting a deformation of the contactor, and (b) providing a drag to eliminate the deformation.
According to the above-described method, an appropriate drag for eliminating the deformation of the contactor can be supplied with accuracy.
REFERENCES:
Derwent Abstract Publication No. RD 422088A, “Wafer Contact Method for Membrane Probe—. . . ” IMC Jun. 10, 1999. (Abstract Only).
Koizumi Daisuke
Maruyama Shigeyuki
Sawamori Akira
Watanabe Naoyuki
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Thompson Craig
LandOfFree
Semiconductor substrate test device and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor substrate test device and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor substrate test device and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2915184