Semiconductor substrate having an isolation region

Details Semiconductor substrate having an isolation region Semiconductor substrate having an isolation region

1998-04-01

2003-02-25

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S647000

Reexamination Certificate

active

06525393

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for manufacturing semiconductor integrated circuits; more particularly to planar isolation of circuitry on a semiconductor substrate, and to a method for forming isolation regions in a semiconductor substrate between regions containing active circuitry.
2. Discussion of Related Art
FIGS. 1A-1F
show a well known method for forming an isolation region in a semiconductor substrate.
In
FIG. 1A
, a semiconductor substrate
10
, such as monocrystalline silicon, is covered with a first buffer layer
12
, such as a 12 nm thick layer of silicon oxide. This covering is typically performed by heating the substrate in a dry oxygen containing atmosphere. A second buffer layer
14
is deposited above this first buffer layer. This may be a 50 nm thick polycrystalline or amorphous silicon layer. A masking layer
16
is deposited over the second buffer layer. This masking layer may be a 160 nm thick layer of silicon nitride. The layers
14
,
16
are deposited by chemical vapor deposition or any other suitable technique.
In
FIG. 1B
, a photographic step followed by an etch has removed the masking layer
16
and the second buffer layer
14
from a selected region
18
, which is the field region. The region
20
which remains covered with the masking and second buffer layers is the active region.
In
FIG. 1C
, the structure is heated in an oxidizing atmosphere of hydrogen and oxygen gases at a temperature of 900 to 1100° C. for a controlled time period, to grow a silicon dioxide isolating layer
22
of field oxide to a desired thickness t
1
, typically in the range 500 to 600 nm.
In an intermediate region
23
, between the active region and the field region, the field oxide
22
penetrates under the masking layer
16
, consuming part of the second buffer layer
14
, to form a region of field oxide having a characteristic shape hereinafter referred to as a “bird's beak”. A notch
26
is formed between the tapering surface of the field oxide
22
and the masking layer
16
. The bird's beak reduces the effective size of the active region, but does not provide an area of acceptable isolation. It is of limited use, and often regarded as wasted space.
During the oxidation step, a thin native oxide is formed over the masking layer
16
. This needs to be removed with an etching step, such as a dip in dilute hydrofluoric acid. As a side effect, some of the field oxide
22
is removed, and now has a thickness of t
2
. The etch causes a hollow
23
a
to be etched in the surface of the field oxide.
In
FIG. 1D
, an isotropic etch step has been used to remove the masking layer. Such an etch may be performed using phosphoric acid to remove a silicon nitride masking layer
16
.
In
FIG. 1E
, the second buffer layer has been removed by a further isotropic etch step, to expose the first buffer layer
12
. A suitable plasma etch may be performed to remove a polycrystalline or amorphous silicon layer.
In
FIG. 1F
, an upper surface
24
of the semiconductor substrate
10
has been exposed by removing the first buffer layer
12
, and with it, some of the field oxide
22
. This etch may be performed using dilute hydrofluoric acid to remove a silicon dioxide first buffer layer. The etch may be carried out for a time long enough to etch 30 nm of silicon dioxide. This ensures that all of the first buffer layer is removed, but also 30 nm of field oxide.
This field oxide then has a thickness t
3
, somewhat less than half of which lies above the upper surface
24
of the semiconductor substrate. There is thus a difference in height of almost ½t
3
between the upper surface of the semiconductor substrate and the upper surface of the field oxide. A sacrificial layer of silicon dioxide is then grown, typically to a thickness of between 10 nm and 80 nm, over the upper surface
24
of the semiconductor substrate, by heating the substrate
10
in a dry, oxygen containing environment, and is later etched away. This serves to clean the upper surface
24
.
FIG. 2
is cross section view of a structure according to the described process. A wide field oxide region
22
is shown. The field oxide thickness t
3
may typically be 450 to 550 nm, giving a difference in height d between the active region and the field region of about 200 nm. The hollow
23
a
is present in the upper surface of the field oxide layer. The position of this hollow approximately corresponds to the position of an edge of the masking layer
16
. It is typically separated from the interface between the field oxide and the upper surface
24
of the substrate by a distance s of about 160 nm. At the lowest point of this hollow, the thickness h of the field oxide is about 160 nm. A minimum width field region
25
a
of width wf equal to the minimum width allowed in the process (about 700 nm) is also shown. It is separated from the first field region
22
by an active region of minimum width wa, such as 400 nm. The minimum width field region
25
a
has a height above the upper surface
24
of the substrate somewhat less than d. A later deposited layer
25
b
, has an upper surface
25
c
, which is very uneven, due to the heights of the field regions below.
Highly planar isolation techniques are needed in current and future integrated circuit fabrication processes. The raised surfaces of field oxide regions in the known process described above cause problems with the control of transistor gate lengths when these gate lengths are less than 0.6 &mgr;m. Current production of processes with a minimum feature size (i.e. transistor gate length) of 0.5 &mgr;m and development of processes with a minimum feature size of 0.35 &mgr;m are impeded by problems caused by reflection of light from slanted edges of the field oxide during the photographic definition of the transistor gate features.
In later steps of the process, referring again to
FIG. 1F
, a gate insulator layer, such as a 10 nm layer of silicon dioxide, is deposited on the upper surface
24
and the field oxide
22
. A conductive layer, such as polycrystalline silicon is then deposited over this gate insulator layer. A photolithography step defines transistor gate electrodes. The definition of the gate electrodes is hindered by the reflection of light from slanting edges of the field oxide. This may cause the final gate electrode to be shorter than desired, as the reflected light may act to expose the edges of the photoresist under opaque portions of the mask. The effect varies with distance from the intermediate region
23
. The gate lengths produced may vary by as much as 0.1 &mgr;m. This represents an intolerable variation for gate lengths of 0.5 &mgr;m or less. To overcome the problem, the masks used define gate lengths 0.1 &mgr;m longer than necessary, meaning that transistor gates far from the field regions will have gate lengths longer than necessary, and the potential speed and current capabilities will not be achieved.
Variations in the transistor gate lengths also lead to variations in several important transistor parameters, such as on-state saturation current, off-state leakage current and channel breakdown or punchthrough voltage.
The difference in height between the active and field regions could cause some defocusing effects in one region due to the limited depth of focus of the photographic step, and step coverage problems in later deposited conductive layers.
During formation of transistors in the semiconductor substrate, spacers are formed on the gate electrode. The difference in height between active and field regions may cause parasitic spacers to be formed on the slanting edges of the field oxide, which later cause problems with interconnect lines running over field regions to connect different active regions together.
Later deposited layers, such as polycrystalline silicon interconnect, metal interconnect and photoresist layers at each masking step are thinner at the point that they cross the intermediate region
23
, due to step coverage problems.
For all of these reasons, it is desired to pr

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