Semiconductor substrate and method of manufacturing semiconducto

Details Semiconductor substrate and method of manufacturing semiconducto Semiconductor substrate and method of manufacturing semiconducto

1998-01-20

2000-10-17

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

257620, 438401, 438462, H01L 23544

Patent

active

061336416

ABSTRACT:
A contact alignment mark (18A) is provided in an interlayer insulating film (17), and a wiring alignment mark (19A) is formed above a gate alignment mark (15A) so that the size of the wiring alignment mark (19A) is slightly larger than the gate alignment mark (15A). At the same time, all the other alignment marks at the lower side are shielded by a shield film (19S). All the alignment marks at the lower side are shielded by the opaque alignment mark and the opaque shield film, whereby the alignment marks can be successively formed while stacked on one another.

REFERENCES:
patent: 5308682 (1994-05-01), Morikawa
patent: 5614767 (1997-03-01), Ohara
patent: 5684333 (1997-11-01), Moriyama
patent: 5933744 (1999-08-01), Chen et al.

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