Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
2000-02-10
2003-03-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
C438S151000, C438S154000, C438S312000, C438S322000
Reexamination Certificate
active
06528377
ABSTRACT:
RELATED APPLICATIONS
This application is related to Ser. No. 6,392,257 filed May 21, 2002 , entitled “Semiconductor Structure, Semiconductor Device, Communicating Device, Integrated Circuit, and Process for Fabricating the Same,” filed of even date and assigned to the Assignee hereof.
FIELD OF THE INVENTION
The invention relates generally to integrated circuit manufacturing and more particularly to a method for processing semiconductor substrates and an apparatus thereof.
BACKGROUND OF THE INVENTION
Integrated circuits are being used in an increasing number of applications that benefit from reduced power consumption. For example, hand-held devices, cellular phones, and other battery operated devices benefit from reduced power consumption characteristics that allow for smaller batteries or longer periods of functionality based on a limited power supply. The need for integrated circuits that exhibit reduced power consumption characteristics has therefore led to the development of semiconductor manufacturing technologies that provide for lower power consumption in integrated circuits.
One technique used to reduce power consumption includes manufacturing the integrated circuits on silicon-on-insulator substrates. Silicon-on-insulator (SOI) structures are known to exhibit favorable power consumption characteristics in comparison with conventional CMOS structures. In addition, SOI structures can produce improved speed characteristics over CMOS technologies as transistor threshold voltages are reduced.
One prior art technique for creating SOI structures includes implanting oxygen into a silicon wafer to form a buried oxide layer. The overlying silicon layer is then annealed in an attempt to restore the crystalline structure of the silicon layer such that it is suitable for device fabrication. However, oxygen implantation often compromises the overlying silicon crystalline structure to a degree that inhibits proper semiconductor device formation due to high defect densities included in the overlying silicon layer. This condition typically persists even after annealing.
In another prior art technique used to generate SOI structures, direct wafer bonding and subsequent separation are used to create the underlying insulating layer. In such prior art techniques, the insulating layer is grown or deposited on a first silicon wafer that is then bonded to a second silicon wafer. A portion of the first silicon wafer is then removed through etching, cleaving, or some other form of physical separation such that a layer of silicon (which had been in an underlying position with respect to the insulating layer on the first wafer) is left to remain overlying the insulating layer on the second wafer. As such, the resulting structure provides pure silicon overlying an insulating layer that is suitable for SOI applications. This prior art technique suffers from a lack of control and results in increased thickness variation of the silicon layer that is formed overlying the insulating layer. For a device manufactured using fully depleted SOI, an important SOI substrate parameter is the thickness of the silicon layer, because thickness variations can directly affect the device threshold voltage. In addition, this prior art technique is costly to implement in a manufacturing environment.
Another issue in semiconductor device fabrication includes the scaling of gate dielectric layers. In some integrated circuit processes, thinner gate dielectric layers are required to achieve desired transistor characteristics based on the dielectric constant of the gate dielectric material used in the process. Thinner gate dielectric layers can lead to problems such as boron penetration, tunneling, etc. Such effects make the reduction of the thickness of silicon dioxide gate dielectric layers below approximately 20 angstroms problematic.
One prior art solution to the problem with gate dielectric scaling includes using high dielectric constant (high-k) dielectric materials to form the gate dielectric. For the purposes of this specification, a high-k material is any dielectric material having a dielectric constant greater than approximately 4.5. By utilizing high-k materials for gate dielectrics in integrated circuit structures, thicker gate dielectric layers can be utilized while maintaining desirable transistor characteristics and avoiding the detrimental effects associated with tunneling, boron penetration, and the like. Although higher k dielectrics are desirable, their formation can be problematic as the interface between the high-k dielectric and silicon often results in a thin layer of silicon oxide being inadvertently formed at the junction. Because silicon oxide has a low dielectric constant, the combination of the low dielectric constant of the silicon oxide with the higher dielectric constant of the high-k dielectric results in undesirably lower overall dielectric constant for the resulting gate dielectric material.
REFERENCES:
patent: 4882300 (1989-11-01), Inoue et al.
patent: 5185689 (1993-02-01), Maniar
patent: 5434742 (1995-07-01), Saito et al.
patent: 5519566 (1996-05-01), Perino et al.
patent: 5589284 (1996-12-01), Summerfelt et al.
patent: 5674366 (1997-10-01), Hayashi et al.
patent: 5731220 (1998-03-01), Tsu et al.
patent: 5801105 (1998-09-01), Yano et al.
patent: 5828080 (1998-10-01), Yano et al.
patent: 5876503 (1999-03-01), Roeder et al.
patent: 5990507 (1999-11-01), Mochizuki et al.
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6020243 (2000-02-01), Wallace et al.
patent: 6054363 (2000-04-01), Sakaguchi et al.
patent: 6242298 (2001-06-01), Kawakubo
patent: WO-96/11887 (1996-04-01), None
patent: 63-198365 (1988-08-01), None
Sakaguchi et al., “ELTRAN by Splitting Porous Si Layers,” ELTRAN Project, Canon, Inc. (2 pgs.).
Yonehara, “ELTRAN; Epitaxial Layer Transfer,” SEMI Si Wafer Symposium, pp. 1-6 (1998).
Kang et al., “Epitaxial Growth of CeO2(100) Films on Si(100) Substrates by Dual Ion Beams Reactive Sputtering,” Elsevier Science Ltd., pp. 225-227 (1998).
Haisma et. al., “Silicon-Wafer Fabrication and (Potential) Applications of Direct-Bonded Silicon,” Philips Journal of Research, pp. 65-89 (1995).
Chikyow et al., “Reaction and regrowth control of CeO2on Si(111) surface for the silicon-on-insulator structure,” American Institute of Physics, pp. 1030-1032 (1994).
Maszara, “Silicon-On-Insulator by Wafer Bonding: A Review,” Journal of the Electrochemical Society, pp. 341-347 (1991).
Abe et al., Wafer Bonding Technique for Silicon-on-Insulator Technology, Solid State Technology, pp. 39-40 (1990).
Asano et al., “An Epitaxial Si/Insulator/Si Structure Prepared by Vacuum Deposition of CaF2and Silicon,” Tokyo Institute of Technology, pp. 143-150 (1982).
Alluri Prasad V.
Cole J. Vernon
Mihopoulos Theodoros
Lally Joseph P.
Motorola Inc.
Rocchegiani Renzo N.
Rodriguez Robert A.
Smith Matthew
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