Semiconductor device manufacturing: process – Gettering of substrate – By implanting or irradiating
Reexamination Certificate
1999-06-14
2001-11-06
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Gettering of substrate
By implanting or irradiating
C438S423000, C438S514000, C438S526000, C257S347000
Reexamination Certificate
active
06313014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor substrate and a method to manufacture a semiconductor substrate, and more specifically to a method to manufacture an SOI (Silicon On Insulator) substrate which has a single-crystal silicon layer on an insulating layer and an SOI substrate manufactured by the method. The present invention relates in particular to an SOI substrate which is manufactured by a method referred to as SIMOX (Separation by Implanted Oxygen) method.
2. Related Background Art
Many researches have been made on formation of single-crystal silicon semiconductor layers on an insulating material since it is widely known as a silicon on insulator (SOI) technique and provides devices which have merits unavailable with ordinary bulk silicon substrates used to manufacture silicon integrated circuits. Speaking concretely, the SOI technique makes it possible to:
1. Facilitate to separate dielectric materials and highly integrate circuits.
2. Obtain excellent resistance to radiation.
3. Reduce floating capacities and accelerate speeds.
4. Omit well process.
5. Prevent latchup.
6. Manufacture completely depletion-mode field effect transistors by thinning silicon layers.
(These merits are described detailedly, for example, in Special Issue: “Single-crystal silicon on non-single-crystal insulators”, edited by G. W. Cullen, Journal of Crystal Growth, Volume 63, No. 3, pp. 429-590 (1983).)
Furthermore, it has been reported in these several years that SOI substrate permits enhancing a speed of MOSFET and lowering its power consumption (IEEE SOI conference 1994).
Furthermore, use of an SOI structure wherein an SOI layer is disposed on a support substrate by way of an insulating layer makes it possible to shorten a time for a device processing step since an element disposed on the insulating layer can be separated in a simpler process than an element formed on a bulk silicon wafer.
That is, the SOI substrate is expected not only to enhance performance of ICs but also to lower total manufacturing cost thereof including a wafer cost and a processing cost as compared with those of MOSFET ICs.
The researches on the SOI substrate has been made vigorously since about 1970s. Researches have been made vigorously on a method which hetero-epitaxially grows single-crystal Si on a sapphire substrate which is an insulating material (SOS: Sapphire On Silicon), a method which forms the SOI structure by isolating a dielectric material by oxidation of porous silicon (FIPOS: Fully Isolation by Porous Oxidized Silicon), a bonding method and an oxygen ion implantation method.
The oxygen ion implantation method is a method which was reported first by K. Izumi and is now referred to as SIMOX (K. Izumi, M. Doken and H. Ariyoshi: Electron Lett. 14, p. 593 (1978)). This method implants oxygen ions into a silicon wafer
103
on the order of 10
17
to 10
18
/cm
2
as shown in
FIG. 11A
(
FIG. 11B
) and then forms an oxide layer
105
by annealing it at a high temperature on the order of 1320° C. in an argon-oxygen atmosphere (FIG.
11
C). As a result, the implanted oxygen ions couple with silicon around a depth corresponding to a projection range (R
p
) of the implanted ions, thereby forming a silicon oxide layer to obtain an SOI substrate
107
. (An SOI substrate manufactured by utilizing the SIMOX will be referred to as an “SIMOX wafer” hereinafter.)
Many reports have been made on the SOI substrate that it enhances a speed of MOSFET and lowers its power consumption (described in detail in Proceedings of 1994 IEEE International Silicon-on-Insulator Conference).
Completely depletion-mode MOSFET manufactured by utilizing the SOI substrate is expected to have faster speed and consume power at a lower rate as a driving power is enhanced.
Furthermore, the SOI structure wherein an insulating layer is disposed under an element allows the element to be separated in a simpler process than an element formed on a bulk silicon wafer, thereby shortening a time for a device processing step.
That is, the SOI structure is expected not only to enhance performance of ICs but also lower total manufacturing cost thereof including wafer costs and processing costs as compared with those of MOSFET ICs disposed on bulk silicon wafers.
A CZ wafer is generally used as a silicon substrate to manufacture an SIMOX wafer. The CZ wafer is a single-crystal silicon substrate which is manufactured by a Czochrlski method.
The CZ wafer contains grown-in defects such as COPs (Crystal Originated Particles) and FPD (Flow Pattern Defect) which are peculiar to a bulk wafer.
The COPs (H. Yamamoto, Problems Posed on Large Diameter Silicon Wafers, 23rd Ultraclean Technology College (August 1996)) and FPD (T. Abe, Extended Abst. Electrochem. Soc. Spring Meeting Vol. 95-1, pp. 596 (May, 1995)) have sizes on the order of approximately 0.1 to 0.2 &mgr;m.
The COPs and FPD will be described in detail later.
When a super LSI was manufactured with the CZ wafer, the defects such as the COPs conventionally influenced little on device characteristics since a device was manufactured with a sufficient margin for the grown-in defects.
Taking DRAMs as an example for which design rules have been changed to specify 0.5 &mgr;m for 16M-DRAM and 0.35 &mgr;m for 64M-DRAM, however, influences due to COPs are more and more remarkable on device characteristics and yields thereof.
Above all, it is said that a design rule will be modified to specify 0.1 to 0.15 &mgr;m for 1G-DRAM.
SUMMARY OF THE INVENTION
A primary object of the present invention is to provide a semiconductor substrate which is scarcely defective and a method to manufacture the semiconductor substrate.
Another object of the present invention is to provide a method to manufacture an SOI substrate having an SOI layer which contains no or a reduced number of defects such as COP, FPD and OSF peculiar to a bulk silicon wafer, and an SOI substrate comprising a buried oxide film which has an excellent quality.
According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor substrate comprising the steps of:
preparing a hydrogen-annealed single-crystal silicon substrate;
forming an ion-implantation layer by implanting ions in the single-crystal silicon substrate; and
forming a buried insulating film in the single-crystal silicon substrate.
According to another aspect of the present invention, there is provided the above-mentioned method for manufacturing a semiconductor substrate, wherein a protective layer is formed on the single-crystal silicon substrate after the hydrogen-annealed single-crystal silicon substrate is prepared and before the ion-implantation layer is formed, and ions are implanted from the side of the protective layer.
According to still another aspect of the present invention, there is provided the above-mentioned method for manufacturing a semiconductor substrate, comprising a step of cleaning the single-crystal silicon substrate before forming the ion-implantation layer.
According to further aspect of the present invention, there is provided the above-mentioned method for manufacturing a semiconductor substrate, wherein the single-crystal silicon substrate is heat-treated in an oxidizing atmosphere after the buried insulating film is formed.
According to further aspect of the present invention, there is provided a semiconductor substrate obtained by the method mentioned in above.
The present invention realizes a process comprised of heat-treating the Si substrate in a reducing atmosphere containing hydrogen, forming an ion-implantation layer in the layer in which COPs and so forth have been decreased or in a portion below the layer, heat-treating the resultant structure to form the buried oxidized Si layer, which makes possible to exclude or decrease the defects peculiar to bulk Si such as CZ wafer. As a result, the present invention enables the yield of the product to be improved. It is said that while a wafer having a larger diameter will be desired in future, the larger the desired diame
Sakaguchi Kiyofumi
Sato Nobuhiko
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Wojciechowicz Edward
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