Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2001-02-22
2002-12-24
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S244000, C257S267000, C257S280000, C257S281000, C257S284000, C257S385000, C257S449000, C257S471000, C257S476000, C257S485000, C438S048000, C438S570000
Reexamination Certificate
active
06498381
ABSTRACT:
BACKGROUND AND SUMMARY
The present invention relates to semiconductor technology.
Some embodiments of the invention facilitate creation of electromagnetic shielding for circuit nodes that carry AC (alternating current) signals. Such shielding advantageously reduces energy losses for the AC signals. The shielding also reduces noise in shielded regions.
Some embodiments allow fabrication of capacitors and capacitor networks in a small area.
According to some aspects of the invention, a circuit manufacturing method comprises:
forming an opening in a first side of a semiconductor substrate, with a plurality of conductive layers overlaying each other in the opening, the conductive layers including a first conductive layer and a second conductive layer overlaying the first conductive layer such that the first and second conductive layers either (i) are separated by an insulating layer in the opening, or (ii) form a P-N junction in the opening, or (iii) form a Schottky junction in the opening;
removing material from a second side of the semiconductor substrate to expose the second conductive layer in the opening on the second side of the substrate.
In some embodiments, the first and second conductive layers are separated by an insulating layer in the opening.
In some embodiments, the first conductive layer shields the substrate from AC signals carried by a contact pad made from the second conductive layer on a wafer backside. Contact pads on the wafer backside can facilitate vertical integration and small scale packaging. See PCT publication WO98/19337 (TruSi Technologies, LLC, May 1998) and U.S. patent application Ser. No. 09/456,225 filed Dec. 6, 1999 by O. Siniaguine et al., now U.S. Pat. No. 6,322,903 issued Nov. 27, 2001. Both of these applications are incorporated herein by reference.
In some embodiments, the first and second conductive layers provide conductive plates of a capacitor.
In some embodiments, the invention provides a circuit structure comprising a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers which overlay sidewalls of the opening, wherein the conductive layers include a first conductive layer and a second conductive layer such that the first and second conductive layers either (i) are separated by an insulating layer in the opening, or (ii) form a P-N junction in the opening, or (iii) form a Schottky junction in the opening; wherein the second conductive layer is exposed on the second side of the opening, and the first conductive layer surrounds the second conductive layer in the opening.
In some embodiments, a circuit manufacturing method comprises:
forming an opening in a first side of a semiconductor substrate;
forming at least three conductive layers overlaying each other in the opening, such that each two consecutive conductive layers either (i) are separated by an insulating layer in the opening, or (ii) form a P-N junction in the opening, or (iii) form a Schottky junction in the opening;
removing material from a second side of the semiconductor substrate to expose at least one of said conductive layers in the opening on the second side of the substrate.
In some embodiments, a circuit structure comprises:
a semiconductor substrate, and an opening passing through the substrate between a first side of the substrate and a second side of the substrate;
at least three conductive layers overlying each other in the opening, such that each two adjacent conductive layers either (i) form a P-N junction in the opening, or (ii) form a Schottky junction in the opening, or (iii) are separated by an insulating layer in the opening;
wherein one of said conductive layers is exposed on the second side.
In some embodiments, a circuit manufacturing method comprises:
forming an opening in a first side of a semiconductor substrate;
forming a plurality of conductive layers overlaying each other in the opening, the conductive layers including a first conductive layer and a second conductive layer overlaying the first conductive layer such that the first and second conductive layers either (i) form a P-N junction, or (ii) form a Schottky diode junction;
removing material from a second side of the semiconductor substrate to expose at least one of the first and second conductive layers on the second side.
In some embodiments, a circuit structure comprises:
a semiconductor substrate, and an opening passing through the substrate between a first side of the substrate and a second side of the substrate;
a plurality of conductive layers overlaying each other in the opening, the conductive layers including first and second conductive layers which either (i) form a P-N junction in the opening, or (ii) form a Schottky junction in the opening;
wherein at least one of the first and second conductive layers is exposed on the second side.
Other features and advantages of the invention are described below.
REFERENCES:
patent: 4353082 (1982-10-01), Chatterjee
patent: 4580331 (1986-04-01), Soclof
patent: 4694561 (1987-09-01), Lebowitz
patent: 4810669 (1989-03-01), Kobayashi
patent: 5016068 (1991-05-01), Mori
patent: 5079615 (1992-01-01), Yamazaki et al.
patent: 5094972 (1992-03-01), Pierce et al.
patent: 5317432 (1994-05-01), Ino
patent: 5385861 (1995-01-01), Bashir et al.
patent: 5804478 (1998-09-01), Nagata et al.
patent: 5843844 (1998-12-01), Miyanaga
patent: 5854501 (1998-12-01), Kao
patent: 6016012 (2000-01-01), Chatila et al.
patent: 6221751 (2001-04-01), Chen et al.
patent: 6322903 (2001-11-01), Siniaguine et al.
patent: WO 98/19337 (1998-05-01), None
Halahan Patrick B.
Siniaguine Oleg
Jackson Jerome
Ortiz Edgardo
Shenker Michael
Skjerven Morrill LLP
Tru-Si Technologies Inc.
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