Semiconductor structures for suppressing gate oxide plasma...

Details Semiconductor structures for suppressing gate oxide plasma... Semiconductor structures for suppressing gate oxide plasma...

1999-09-14

2001-08-21

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S585000, C257S328000, C257S356000, C257S508000

Reexamination Certificate

active

06277708

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor circuits and, more particularly, to semiconductor structures for protecting transistor gate oxides during plasma etch fabrication operations.
2. Description of the Related Art
As is well known in the art, semiconductor devices are fabricated over a semiconductor substrate that is subjected to numerous processing operations. By way of example, a semiconductor device is typically subjected to several plasma etching operations, which are designed to pattern the various substrate, oxide and metallization layers and construct the desired circuit layout. Although plasma etching has become the etching process of choice, the intense energies used to create the etching plasma has had a degrading effect on thin sensitive gate oxides that lie under gate electrodes of a given circuit design. Specifically, the plasma that is generated in etching chambers is designed to bombard a layer being etched with a high concentration of electrons and positively charged ions. Unfortunately, these electrons and positively charged ions are known to induce intense currents through the gate oxides, which necessarily produce oxide degrading traps in the gate oxides.
With this in mind,
FIG. 1A
shows a cross-sectional view of a semiconductor substrate
100
during a plasma etch
102
operation. In this example, the semiconductor substrate
100
is patterned with a photoresist mask
108
, which enables patterning of a polysilicon gate
106
that lies over a gate oxide
104
. As mentioned above, when the plasma etch operation is performed, a large amount of positively charged ions and negatively charged electrons are caused to come into contact with exposed surface areas of the polysilicon gate
106
. When this happens, strong electrical currents are caused to flow between the polysilicon gate
106
, through the gate oxide
104
, and into the substrate
100
.
Unfortunately, during normal plasma etch operations, these electrical currents can become quite substantial, and therefore may cause what are known as “traps” inside the gate oxide
104
. These traps that are formed inside the chemical bonds of the gate oxide
104
therefore detrimentally degrade the gate oxide
104
, which can lead to gate current leakage. For example, properly functioning transistor devices require gate oxides
104
that adequately isolate the polysilicon gate
106
from the substrate
100
. However, when the gate oxide
104
accumulates a large amount of trap charging, the degraded gate oxide
104
may no longer insulate the polysilicon gate
106
from the semiconductor substrate
100
and leakage currents will occur through the gate oxide
104
.
FIG. 1B
shows a more detailed diagram of the polysilicon gate
106
that includes a silicided metallization layer
106
a.
The polysilicon gate
106
is now shown in contact with a degraded gate oxide
104
′. On either side of the polysilicon gate
106
and the degraded gate oxide
104
′, are oxide spacers
109
. The oxide spacers
109
sit partially over the diffusion regions
112
. In a properly functioning transistor gate, the gate oxide is supposed to electrically isolate the polysilicon gate
106
from the substrate
100
. However, when the degraded gate oxide
104
′ builds up a large amount of chemical bond altering traps due to the repeated electrical exposure to plasma etch operations, the degraded gate oxide
104
′ will no longer perform its isolation function.
As shown, a channel region
110
is formed between the diffusion regions
112
in the semiconductor substrate
100
. In a properly functioning device, the transistor having the polysilicon gate
106
can control the channel region
110
to be in an ON state or OFF state depending on the voltage applied to the polysilicon gate
106
. However, when the degraded gate oxide
104
′ no longer isolates the polysilicon gate
106
from the substrate
100
, the polysilicon gate loses control over the channel region
110
. As can be appreciated, when this happens, the semiconductor device will fail to operate in its designed manner. As a result, not only will a single transistor fail to operate for its intended purpose, but an entire semiconductor chip may fail to operate properly and perform its desired functional operations.
It should also be appreciated that the gate oxide
104
is susceptible to degradation during each stage that a plasma etching operation is performed, and electrical conduction between the plasma etching and the gate oxide
104
exists. By way of example, the oxide spacers
109
are generally formed by depositing an oxide layer over the entire surface of a wafer, and then subsequently performing a plasma etch until this oxide spacers
109
remain. However, when such oxide spacer etching is performed, the polysilicon gate
106
will come into electrical contact with the plasma etching that is used to perform the oxide spacer formation.
Thus, additional plasma induced currents “I” will unfortunately cause further trap formation in the degraded gate oxide
104
′. Additionally, when subsequent via hole etching operations and metallization interconnect patterning operations are performed, that plasma etching will also come into electrical contact with the polysilicon gate
106
, which will then conduct additional current through the degraded gate oxide
104
′, thereby producing additional traps in the degraded gate oxide
104
′.
As shown in
FIG. 1C
, when a via hole is plasma etched in an intermetal dielectric
116
, the plasma ions and electrons will also come into contact with the silicided metallization layer
106
a
that lies over the polysilicon gate
106
. As a result, oxide destructive currents will also be caused to occur through the degraded gate oxide
104
′. Additionally, when a patterned metallization line
118
is formed over and in contact with an electrical tungsten plug
117
, the ions and electrons produced by the plasma patterning will again cause currents to flow through the degraded gate oxide
104
′.
In prior art attempts to divert plasma induced currents away from the gate oxide
104
, diode structures have been fabricated beside sensitive transistor gate structures. As shown in
FIG. 1D
, the diode structure includes an N+well
150
which interfaces with a P-type substrate to form a solid state diode structure. The diode structure is a leaky diode structure which allows a current I
D
to flow away from the gate oxide
104
and down a via
117
a
during plasma etching.
Unfortunately, fabricating these diode structures beside sensitive transistor devices has the downside of requiring a substantial amount of additional chip space. This is because such diode designs are typically only fabricated to suppress large currents produced when transistor gates have large contact surfaces
106
b
as shown in FIG.
1
E. These large contact surfaces
106
b
are known to cause “antenna effects,” which also detrimentally produce very large oxide destructive currents “I”.
Furthermore, the diode structure of
FIG. 1D
will not assist in protecting the gate oxide
104
until interconnect layers, such as the patterned metallization layer
118
′ is formed. That is, the diode structure will not protect the gate oxide
104
′ during the polysilicon gate
106
patterning, during the spacer
109
formation, and when a via hole is etched through the intermetal oxide
116
in order to form a conductive via
117
. Accordingly, by the time a protection diode structure is formed beside a sensitive transistor device, the gate oxide
104
will already have been exposed to a substantial amount of destructive current induced by the plasma patterning operations.
In view of the foregoing, there is a need for compact protection device structures which assist in protecting gate oxides from the formation of traps and subsequent oxide degradation. There is also a need for protecting the gate oxides in order to prevent leakage currents and malfunctioni

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