Semiconductor structures and packaging methods

Details Semiconductor structures and packaging methods Semiconductor structures and packaging methods

1996-12-10

2000-02-22

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Groove

257623, 257626, 257618, 257619, 257620, 257632, H01L 2906

Patent

active

060283475

ABSTRACT:
A semiconductor structure having: semiconductor devices formed in an inner region of a semiconductor chip; a seal ring formed in the chip and disposed about the inner region; and, a plurality of trenches formed along a surface of the chip. The trenches are disposed in a corner region of the chip. A portion of the seal ring is disposed between the trenches and the inner region of the chip. The trenches are disposed along axes oblique to outer edges of the chip. A method is provided for encapsulating a semiconductor chip. The method includes the steps of: providing a semiconductor chip having active semiconductor devices in an inner region of the semiconductor chip and a seal ring in the chip about the inner region; and, forming a plurality of trenches in the chip, a portion of the seal ring being formed between the trenches and the inner region of the chip. A cover is formed having bottom portions in the trenches and on the passivation layer. In particular, the cover is formed by flowing plastic material over the passivation layer and into the trenches to fill such trenches with such plastic material.

REFERENCES:
patent: 5763936 (1998-06-01), Yamaha et al.
patent: 5831330 (1998-11-01), Chang

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