Semiconductor structure including laminated isolation region

Details Semiconductor structure including laminated isolation region Semiconductor structure including laminated isolation region

2008-06-20

2010-10-19

Menz, Laura M (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S384000, C257S330000

Reexamination Certificate

active

07816760

ABSTRACT:
A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U shaped dielectric liner layer located upon the lower lying dielectric plug layer and partially filling the recess; and (3) an upper lying dielectric plug layer located upon the U shaped dielectric liner layer and completely filling the recess. The isolation region provides for sidewall coverage of the isolation trench, thus eliminating some types of leakage paths.

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