Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Utility Patent
1998-08-07
2001-01-02
Carroll, J. (Department: 2811)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S216000, C438S275000, C438S287000
Utility Patent
active
06168958
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to semiconductor structures, and more particularly, to a semiconductor structure having multiple thicknesses of high-K gate dielectrics.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
A typical MOS semiconductor device generally includes a gate electrode, which acts as a conductor, to which an input signal is typically applied via a gate terminal. Heavily doped source/drain regions are formed in a semiconductor substrate and are respectively connected to source and drain terminals. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The channel is typically lightly doped with a dopant type opposite that of the source/drain regions. The gate electrode is physically separated from the semiconductor substrate by a gate insulating layer, typically an oxide layer such as SiO
2
. The insulating layer is provided to prevent current from flowing between the gate electrode and the source/drain regions or channel regions.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source region/drain regions. In this manner an electric field controls the current flow through the channel region. This type of device is commonly referred to as a MOS field-effect-transistors (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate ever increasing numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) and in order to form a larger number of devices on a given surface area, the structure of the devices and fabrication techniques used to make such devices must be altered.
One important step in the manufacture of MOS devices is the formation of the gate insulating layer. The gate insulating layer is typically formed by growing an oxide, typically SiO
2
, over the surface of the substrate. It is important to carefully control the growth of the gate oxide layer because the thickness and uniformity of the gate oxide layer can significantly impact the overall operation of the device being formed. For example, the drive current in a MOS transistor is inversely proportional to the gate oxide thickness at a given set of terminal voltages. Accordingly, it is normally desired to increase the drive current of the transistor by making the gate oxide as thin as possible, taking into consideration the oxide breakdown and reliability considerations of the process and technology being used.
The above described conventional techniques for forming gate oxide layers impose limitations on the minimum thickness of the gate oxide layer and on the ability to control the uniformity of the gate oxide layer. As the thresholds for minimum thickness and uniformity control are reached, the ability to further scale down the semiconductor devices is hindered.
SUMMARY OF THE INVENTION
Generally, the present invention relates to a semiconductor structure having multiple thicknesses of high-K gate dielectrics. In one embodiment, a semiconductor structure is provided that includes a substrate, and a high permittivity layer is disposed on the substrate which has two or more areas with different thicknesses. A plurality of gate electrodes are disposed in the two or more areas on the high permittivity layer.
In another embodiment, a process is provided for constructing a semiconductor structure. The process includes depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness. A first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness. Selected portions of the high permittivity layer are then removed, whereby the high permittivity layer is reduced to a second thickness. Then a second set of gate electrodes are formed on the selected portions of the high permittivity layer having the second thickness.
A process for forming a semiconductor structure on a silicon substrate is provided in another embodiment. The process comprises depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness of about 100-500 Å and a dielectric constant of at least 20. A gate conductive layer is deposited on the high permittivity layer, and selected portions of the gate conductive layer are etched, whereby a first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness. Further, etching selected portions of the high permittivity layer reduces the high permittivity layer to a second thickness. A second set of gate electrodes is then formed on the selected portions of the high permittivity layer having the second thickness.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
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Fulford H. Jim
Gardner Mark I.
May Charles E.
Advanced Micro Devices , Inc.
Carroll J.
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