Semiconductor structure having a barrier layer disposed within o

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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257752, 257763, 257767, H01L 2968, H01L 2934, H01L 2906

Patent

active

052668355

ABSTRACT:
A method for connecting devices on an integrated circuit substrate to a metallization layer, wherein a thin layer of a dielectric material is deposited on the substrate, and openings are formed in the dielectric layer wherein electrical connection is to be made to the substrate. A metal barrier layer then is deposited selectively in the openings of the dielectric layer, the barrier layer completely covering the exposed portions of the substrate. A pillar metal layer then may be deposited as a blanket coating over the dielectric layer and over the portions of he barrier layer covering the exposed portions of the substrate. The pillar metal layer is etched for forming metal pillars extending from the exposed portions of the substrate. The substrate then is planarized by depositing a dielectric layer and etching it back for exposing the pillars for coupling to a later deposited metallization layer.

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